1/* 2 * TQM 8540 Device Tree Source 3 * 4 * Copyright 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "tqc,tqm8540"; 16 compatible = "tqc,tqm8540"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 ethernet2 = &enet2; 24 serial0 = &serial0; 25 serial1 = &serial1; 26 pci0 = &pci0; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 PowerPC,8540@0 { 34 device_type = "cpu"; 35 reg = <0>; 36 d-cache-line-size = <32>; 37 i-cache-line-size = <32>; 38 d-cache-size = <32768>; 39 i-cache-size = <32768>; 40 timebase-frequency = <0>; 41 bus-frequency = <0>; 42 clock-frequency = <0>; 43 next-level-cache = <&L2>; 44 }; 45 }; 46 47 memory { 48 device_type = "memory"; 49 reg = <0x00000000 0x10000000>; 50 }; 51 52 soc@e0000000 { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 device_type = "soc"; 56 ranges = <0x0 0xe0000000 0x100000>; 57 reg = <0xe0000000 0x200>; 58 bus-frequency = <0>; 59 compatible = "fsl,mpc8540-immr", "simple-bus"; 60 61 memory-controller@2000 { 62 compatible = "fsl,8540-memory-controller"; 63 reg = <0x2000 0x1000>; 64 interrupt-parent = <&mpic>; 65 interrupts = <18 2>; 66 }; 67 68 L2: l2-cache-controller@20000 { 69 compatible = "fsl,8540-l2-cache-controller"; 70 reg = <0x20000 0x1000>; 71 cache-line-size = <32>; 72 cache-size = <0x40000>; // L2, 256K 73 interrupt-parent = <&mpic>; 74 interrupts = <16 2>; 75 }; 76 77 i2c@3000 { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 cell-index = <0>; 81 compatible = "fsl-i2c"; 82 reg = <0x3000 0x100>; 83 interrupts = <43 2>; 84 interrupt-parent = <&mpic>; 85 dfsrr; 86 87 dtt@50 { 88 compatible = "national,lm75"; 89 reg = <0x50>; 90 }; 91 92 rtc@68 { 93 compatible = "dallas,ds1337"; 94 reg = <0x68>; 95 }; 96 }; 97 98 dma@21300 { 99 #address-cells = <1>; 100 #size-cells = <1>; 101 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; 102 reg = <0x21300 0x4>; 103 ranges = <0x0 0x21100 0x200>; 104 cell-index = <0>; 105 dma-channel@0 { 106 compatible = "fsl,mpc8540-dma-channel", 107 "fsl,eloplus-dma-channel"; 108 reg = <0x0 0x80>; 109 cell-index = <0>; 110 interrupt-parent = <&mpic>; 111 interrupts = <20 2>; 112 }; 113 dma-channel@80 { 114 compatible = "fsl,mpc8540-dma-channel", 115 "fsl,eloplus-dma-channel"; 116 reg = <0x80 0x80>; 117 cell-index = <1>; 118 interrupt-parent = <&mpic>; 119 interrupts = <21 2>; 120 }; 121 dma-channel@100 { 122 compatible = "fsl,mpc8540-dma-channel", 123 "fsl,eloplus-dma-channel"; 124 reg = <0x100 0x80>; 125 cell-index = <2>; 126 interrupt-parent = <&mpic>; 127 interrupts = <22 2>; 128 }; 129 dma-channel@180 { 130 compatible = "fsl,mpc8540-dma-channel", 131 "fsl,eloplus-dma-channel"; 132 reg = <0x180 0x80>; 133 cell-index = <3>; 134 interrupt-parent = <&mpic>; 135 interrupts = <23 2>; 136 }; 137 }; 138 139 mdio@24520 { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 compatible = "fsl,gianfar-mdio"; 143 reg = <0x24520 0x20>; 144 145 phy1: ethernet-phy@1 { 146 interrupt-parent = <&mpic>; 147 interrupts = <8 1>; 148 reg = <1>; 149 device_type = "ethernet-phy"; 150 }; 151 phy2: ethernet-phy@2 { 152 interrupt-parent = <&mpic>; 153 interrupts = <8 1>; 154 reg = <2>; 155 device_type = "ethernet-phy"; 156 }; 157 phy3: ethernet-phy@3 { 158 interrupt-parent = <&mpic>; 159 interrupts = <8 1>; 160 reg = <3>; 161 device_type = "ethernet-phy"; 162 }; 163 tbi0: tbi-phy@11 { 164 reg = <0x11>; 165 device_type = "tbi-phy"; 166 }; 167 }; 168 169 mdio@25520 { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 compatible = "fsl,gianfar-tbi"; 173 reg = <0x25520 0x20>; 174 175 tbi1: tbi-phy@11 { 176 reg = <0x11>; 177 device_type = "tbi-phy"; 178 }; 179 }; 180 181 mdio@26520 { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 compatible = "fsl,gianfar-tbi"; 185 reg = <0x26520 0x20>; 186 187 tbi2: tbi-phy@11 { 188 reg = <0x11>; 189 device_type = "tbi-phy"; 190 }; 191 }; 192 193 enet0: ethernet@24000 { 194 cell-index = <0>; 195 device_type = "network"; 196 model = "TSEC"; 197 compatible = "gianfar"; 198 reg = <0x24000 0x1000>; 199 local-mac-address = [ 00 00 00 00 00 00 ]; 200 interrupts = <29 2 30 2 34 2>; 201 interrupt-parent = <&mpic>; 202 phy-handle = <&phy2>; 203 }; 204 205 enet1: ethernet@25000 { 206 cell-index = <1>; 207 device_type = "network"; 208 model = "TSEC"; 209 compatible = "gianfar"; 210 reg = <0x25000 0x1000>; 211 local-mac-address = [ 00 00 00 00 00 00 ]; 212 interrupts = <35 2 36 2 40 2>; 213 interrupt-parent = <&mpic>; 214 phy-handle = <&phy1>; 215 }; 216 217 enet2: ethernet@26000 { 218 cell-index = <2>; 219 device_type = "network"; 220 model = "FEC"; 221 compatible = "gianfar"; 222 reg = <0x26000 0x1000>; 223 local-mac-address = [ 00 00 00 00 00 00 ]; 224 interrupts = <41 2>; 225 interrupt-parent = <&mpic>; 226 phy-handle = <&phy3>; 227 }; 228 229 serial0: serial@4500 { 230 cell-index = <0>; 231 device_type = "serial"; 232 compatible = "ns16550"; 233 reg = <0x4500 0x100>; // reg base, size 234 clock-frequency = <0>; // should we fill in in uboot? 235 interrupts = <42 2>; 236 interrupt-parent = <&mpic>; 237 }; 238 239 serial1: serial@4600 { 240 cell-index = <1>; 241 device_type = "serial"; 242 compatible = "ns16550"; 243 reg = <0x4600 0x100>; // reg base, size 244 clock-frequency = <0>; // should we fill in in uboot? 245 interrupts = <42 2>; 246 interrupt-parent = <&mpic>; 247 }; 248 249 mpic: pic@40000 { 250 interrupt-controller; 251 #address-cells = <0>; 252 #interrupt-cells = <2>; 253 reg = <0x40000 0x40000>; 254 device_type = "open-pic"; 255 compatible = "chrp,open-pic"; 256 }; 257 }; 258 259 pci0: pci@e0008000 { 260 cell-index = <0>; 261 #interrupt-cells = <1>; 262 #size-cells = <2>; 263 #address-cells = <3>; 264 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 265 device_type = "pci"; 266 reg = <0xe0008000 0x1000>; 267 clock-frequency = <66666666>; 268 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 269 interrupt-map = < 270 /* IDSEL 28 */ 271 0xe000 0 0 1 &mpic 2 1 272 0xe000 0 0 2 &mpic 3 1>; 273 274 interrupt-parent = <&mpic>; 275 interrupts = <24 2>; 276 bus-range = <0 0>; 277 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 278 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 279 }; 280}; 281