1/* 2 * TQM5200 board Device Tree Source 3 * 4 * Copyright (C) 2007 Semihalf 5 * Marian Balakowicz <m8@semihalf.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/dts-v1/; 14 15/ { 16 model = "tqc,tqm5200"; 17 compatible = "tqc,tqm5200"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 PowerPC,5200@0 { 26 device_type = "cpu"; 27 reg = <0>; 28 d-cache-line-size = <32>; 29 i-cache-line-size = <32>; 30 d-cache-size = <0x4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K 32 timebase-frequency = <0>; // from bootloader 33 bus-frequency = <0>; // from bootloader 34 clock-frequency = <0>; // from bootloader 35 }; 36 }; 37 38 memory { 39 device_type = "memory"; 40 reg = <0x00000000 0x04000000>; // 64MB 41 }; 42 43 soc5200@f0000000 { 44 #address-cells = <1>; 45 #size-cells = <1>; 46 compatible = "fsl,mpc5200-immr"; 47 ranges = <0 0xf0000000 0x0000c000>; 48 reg = <0xf0000000 0x00000100>; 49 bus-frequency = <0>; // from bootloader 50 system-frequency = <0>; // from bootloader 51 52 cdm@200 { 53 compatible = "fsl,mpc5200-cdm"; 54 reg = <0x200 0x38>; 55 }; 56 57 mpc5200_pic: interrupt-controller@500 { 58 // 5200 interrupts are encoded into two levels; 59 interrupt-controller; 60 #interrupt-cells = <3>; 61 compatible = "fsl,mpc5200-pic"; 62 reg = <0x500 0x80>; 63 }; 64 65 timer@600 { // General Purpose Timer 66 compatible = "fsl,mpc5200-gpt"; 67 reg = <0x600 0x10>; 68 interrupts = <1 9 0>; 69 interrupt-parent = <&mpc5200_pic>; 70 fsl,has-wdt; 71 }; 72 73 can@900 { 74 compatible = "fsl,mpc5200-mscan"; 75 interrupts = <2 17 0>; 76 interrupt-parent = <&mpc5200_pic>; 77 reg = <0x900 0x80>; 78 }; 79 80 can@980 { 81 compatible = "fsl,mpc5200-mscan"; 82 interrupts = <2 18 0>; 83 interrupt-parent = <&mpc5200_pic>; 84 reg = <0x980 0x80>; 85 }; 86 87 gpio@b00 { 88 compatible = "fsl,mpc5200-gpio"; 89 reg = <0xb00 0x40>; 90 interrupts = <1 7 0>; 91 interrupt-parent = <&mpc5200_pic>; 92 }; 93 94 usb@1000 { 95 compatible = "fsl,mpc5200-ohci","ohci-be"; 96 reg = <0x1000 0xff>; 97 interrupts = <2 6 0>; 98 interrupt-parent = <&mpc5200_pic>; 99 }; 100 101 dma-controller@1200 { 102 compatible = "fsl,mpc5200-bestcomm"; 103 reg = <0x1200 0x80>; 104 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 105 3 4 0 3 5 0 3 6 0 3 7 0 106 3 8 0 3 9 0 3 10 0 3 11 0 107 3 12 0 3 13 0 3 14 0 3 15 0>; 108 interrupt-parent = <&mpc5200_pic>; 109 }; 110 111 xlb@1f00 { 112 compatible = "fsl,mpc5200-xlb"; 113 reg = <0x1f00 0x100>; 114 }; 115 116 serial@2000 { // PSC1 117 device_type = "serial"; 118 compatible = "fsl,mpc5200-psc-uart"; 119 port-number = <0>; // Logical port assignment 120 reg = <0x2000 0x100>; 121 interrupts = <2 1 0>; 122 interrupt-parent = <&mpc5200_pic>; 123 }; 124 125 serial@2200 { // PSC2 126 device_type = "serial"; 127 compatible = "fsl,mpc5200-psc-uart"; 128 port-number = <1>; // Logical port assignment 129 reg = <0x2200 0x100>; 130 interrupts = <2 2 0>; 131 interrupt-parent = <&mpc5200_pic>; 132 }; 133 134 serial@2400 { // PSC3 135 device_type = "serial"; 136 compatible = "fsl,mpc5200-psc-uart"; 137 port-number = <2>; // Logical port assignment 138 reg = <0x2400 0x100>; 139 interrupts = <2 3 0>; 140 interrupt-parent = <&mpc5200_pic>; 141 }; 142 143 ethernet@3000 { 144 device_type = "network"; 145 compatible = "fsl,mpc5200-fec"; 146 reg = <0x3000 0x400>; 147 local-mac-address = [ 00 00 00 00 00 00 ]; 148 interrupts = <2 5 0>; 149 interrupt-parent = <&mpc5200_pic>; 150 phy-handle = <&phy0>; 151 }; 152 153 mdio@3000 { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 compatible = "fsl,mpc5200-mdio"; 157 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 158 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 159 interrupt-parent = <&mpc5200_pic>; 160 161 phy0: ethernet-phy@0 { 162 device_type = "ethernet-phy"; 163 reg = <0>; 164 }; 165 }; 166 167 ata@3a00 { 168 compatible = "fsl,mpc5200-ata"; 169 reg = <0x3a00 0x100>; 170 interrupts = <2 7 0>; 171 interrupt-parent = <&mpc5200_pic>; 172 }; 173 174 i2c@3d40 { 175 #address-cells = <1>; 176 #size-cells = <0>; 177 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 178 reg = <0x3d40 0x40>; 179 interrupts = <2 16 0>; 180 interrupt-parent = <&mpc5200_pic>; 181 fsl5200-clocking; 182 183 rtc@68 { 184 device_type = "rtc"; 185 compatible = "dallas,ds1307"; 186 reg = <0x68>; 187 }; 188 }; 189 190 sram@8000 { 191 compatible = "fsl,mpc5200-sram"; 192 reg = <0x8000 0x4000>; 193 }; 194 }; 195 196 lpb { 197 model = "fsl,lpb"; 198 compatible = "fsl,lpb"; 199 #address-cells = <2>; 200 #size-cells = <1>; 201 ranges = <0 0 0xfc000000 0x02000000>; 202 203 flash@0,0 { 204 compatible = "cfi-flash"; 205 reg = <0 0 0x02000000>; 206 bank-width = <4>; 207 device-width = <2>; 208 #size-cells = <1>; 209 #address-cells = <1>; 210 }; 211 }; 212 213 pci@f0000d00 { 214 #interrupt-cells = <1>; 215 #size-cells = <2>; 216 #address-cells = <3>; 217 device_type = "pci"; 218 compatible = "fsl,mpc5200-pci"; 219 reg = <0xf0000d00 0x100>; 220 interrupt-map-mask = <0xf800 0 0 7>; 221 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 222 0xc000 0 0 2 &mpc5200_pic 0 0 3 223 0xc000 0 0 3 &mpc5200_pic 0 0 3 224 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 225 clock-frequency = <0>; // From boot loader 226 interrupts = <2 8 0 2 9 0 2 10 0>; 227 interrupt-parent = <&mpc5200_pic>; 228 bus-range = <0 0>; 229 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 230 0x02000000 0 0x90000000 0x90000000 0 0x10000000 231 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; 232 }; 233}; 234