1/* 2 * TQM5200 board Device Tree Source 3 * 4 * Copyright (C) 2007 Semihalf 5 * Marian Balakowicz <m8@semihalf.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/dts-v1/; 14 15/ { 16 model = "tqc,tqm5200"; 17 compatible = "tqc,tqm5200"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 PowerPC,5200@0 { 26 device_type = "cpu"; 27 reg = <0>; 28 d-cache-line-size = <32>; 29 i-cache-line-size = <32>; 30 d-cache-size = <0x4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K 32 timebase-frequency = <0>; // from bootloader 33 bus-frequency = <0>; // from bootloader 34 clock-frequency = <0>; // from bootloader 35 }; 36 }; 37 38 memory { 39 device_type = "memory"; 40 reg = <0x00000000 0x04000000>; // 64MB 41 }; 42 43 soc5200@f0000000 { 44 #address-cells = <1>; 45 #size-cells = <1>; 46 compatible = "fsl,mpc5200-immr"; 47 ranges = <0 0xf0000000 0x0000c000>; 48 reg = <0xf0000000 0x00000100>; 49 bus-frequency = <0>; // from bootloader 50 system-frequency = <0>; // from bootloader 51 52 cdm@200 { 53 compatible = "fsl,mpc5200-cdm"; 54 reg = <0x200 0x38>; 55 }; 56 57 mpc5200_pic: interrupt-controller@500 { 58 // 5200 interrupts are encoded into two levels; 59 interrupt-controller; 60 #interrupt-cells = <3>; 61 compatible = "fsl,mpc5200-pic"; 62 reg = <0x500 0x80>; 63 }; 64 65 timer@600 { // General Purpose Timer 66 compatible = "fsl,mpc5200-gpt"; 67 reg = <0x600 0x10>; 68 interrupts = <1 9 0>; 69 interrupt-parent = <&mpc5200_pic>; 70 fsl,has-wdt; 71 }; 72 73 gpio@b00 { 74 compatible = "fsl,mpc5200-gpio"; 75 reg = <0xb00 0x40>; 76 interrupts = <1 7 0>; 77 interrupt-parent = <&mpc5200_pic>; 78 }; 79 80 usb@1000 { 81 compatible = "fsl,mpc5200-ohci","ohci-be"; 82 reg = <0x1000 0xff>; 83 interrupts = <2 6 0>; 84 interrupt-parent = <&mpc5200_pic>; 85 }; 86 87 dma-controller@1200 { 88 compatible = "fsl,mpc5200-bestcomm"; 89 reg = <0x1200 0x80>; 90 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 91 3 4 0 3 5 0 3 6 0 3 7 0 92 3 8 0 3 9 0 3 10 0 3 11 0 93 3 12 0 3 13 0 3 14 0 3 15 0>; 94 interrupt-parent = <&mpc5200_pic>; 95 }; 96 97 xlb@1f00 { 98 compatible = "fsl,mpc5200-xlb"; 99 reg = <0x1f00 0x100>; 100 }; 101 102 serial@2000 { // PSC1 103 device_type = "serial"; 104 compatible = "fsl,mpc5200-psc-uart"; 105 port-number = <0>; // Logical port assignment 106 reg = <0x2000 0x100>; 107 interrupts = <2 1 0>; 108 interrupt-parent = <&mpc5200_pic>; 109 }; 110 111 serial@2200 { // PSC2 112 device_type = "serial"; 113 compatible = "fsl,mpc5200-psc-uart"; 114 port-number = <1>; // Logical port assignment 115 reg = <0x2200 0x100>; 116 interrupts = <2 2 0>; 117 interrupt-parent = <&mpc5200_pic>; 118 }; 119 120 serial@2400 { // PSC3 121 device_type = "serial"; 122 compatible = "fsl,mpc5200-psc-uart"; 123 port-number = <2>; // Logical port assignment 124 reg = <0x2400 0x100>; 125 interrupts = <2 3 0>; 126 interrupt-parent = <&mpc5200_pic>; 127 }; 128 129 ethernet@3000 { 130 device_type = "network"; 131 compatible = "fsl,mpc5200-fec"; 132 reg = <0x3000 0x400>; 133 local-mac-address = [ 00 00 00 00 00 00 ]; 134 interrupts = <2 5 0>; 135 interrupt-parent = <&mpc5200_pic>; 136 phy-handle = <&phy0>; 137 }; 138 139 mdio@3000 { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 compatible = "fsl,mpc5200-mdio"; 143 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 144 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 145 interrupt-parent = <&mpc5200_pic>; 146 147 phy0: ethernet-phy@0 { 148 device_type = "ethernet-phy"; 149 reg = <0>; 150 }; 151 }; 152 153 ata@3a00 { 154 compatible = "fsl,mpc5200-ata"; 155 reg = <0x3a00 0x100>; 156 interrupts = <2 7 0>; 157 interrupt-parent = <&mpc5200_pic>; 158 }; 159 160 i2c@3d40 { 161 #address-cells = <1>; 162 #size-cells = <0>; 163 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 164 reg = <0x3d40 0x40>; 165 interrupts = <2 16 0>; 166 interrupt-parent = <&mpc5200_pic>; 167 fsl5200-clocking; 168 169 rtc@68 { 170 device_type = "rtc"; 171 compatible = "dallas,ds1307"; 172 reg = <0x68>; 173 }; 174 }; 175 176 sram@8000 { 177 compatible = "fsl,mpc5200-sram"; 178 reg = <0x8000 0x4000>; 179 }; 180 }; 181 182 lpb { 183 model = "fsl,lpb"; 184 compatible = "fsl,lpb"; 185 #address-cells = <2>; 186 #size-cells = <1>; 187 ranges = <0 0 0xfc000000 0x02000000>; 188 189 flash@0,0 { 190 compatible = "cfi-flash"; 191 reg = <0 0 0x02000000>; 192 bank-width = <4>; 193 device-width = <2>; 194 #size-cells = <1>; 195 #address-cells = <1>; 196 }; 197 }; 198 199 pci@f0000d00 { 200 #interrupt-cells = <1>; 201 #size-cells = <2>; 202 #address-cells = <3>; 203 device_type = "pci"; 204 compatible = "fsl,mpc5200-pci"; 205 reg = <0xf0000d00 0x100>; 206 interrupt-map-mask = <0xf800 0 0 7>; 207 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 208 0xc000 0 0 2 &mpc5200_pic 0 0 3 209 0xc000 0 0 3 &mpc5200_pic 0 0 3 210 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 211 clock-frequency = <0>; // From boot loader 212 interrupts = <2 8 0 2 9 0 2 10 0>; 213 interrupt-parent = <&mpc5200_pic>; 214 bus-range = <0 0>; 215 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 216 0x02000000 0 0x90000000 0x90000000 0 0x10000000 217 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; 218 }; 219}; 220