1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC8555-based STx GP3 Device Tree Source
4 *
5 * Copyright 2006, 2008 Freescale Semiconductor Inc.
6 *
7 * Copyright 2010 Silicon Turnkey Express LLC.
8 */
9
10/dts-v1/;
11
12/ {
13	model = "stx,gp3";
14        compatible = "stx,gp3-8560", "stx,gp3";
15	#address-cells = <1>;
16	#size-cells = <1>;
17
18	aliases {
19		ethernet0 = &enet0;
20		ethernet1 = &enet1;
21		serial0 = &serial0;
22		serial1 = &serial1;
23		pci0 = &pci0;
24	};
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		PowerPC,8555@0 {
31			device_type = "cpu";
32			reg = <0x0>;
33			d-cache-line-size = <32>;	// 32 bytes
34			i-cache-line-size = <32>;	// 32 bytes
35			d-cache-size = <0x8000>;		// L1, 32K
36			i-cache-size = <0x8000>;		// L1, 32K
37			timebase-frequency = <0>;	//  33 MHz, from uboot
38			bus-frequency = <0>;	// 166 MHz
39			clock-frequency = <0>;	// 825 MHz, from uboot
40			next-level-cache = <&L2>;
41		};
42	};
43
44	memory {
45		device_type = "memory";
46		reg = <0x00000000 0x10000000>;
47	};
48
49	soc8555@e0000000 {
50		#address-cells = <1>;
51		#size-cells = <1>;
52		device_type = "soc";
53		compatible = "simple-bus";
54		ranges = <0x0 0xe0000000 0x100000>;
55		bus-frequency = <0>;
56
57		ecm-law@0 {
58			compatible = "fsl,ecm-law";
59			reg = <0x0 0x1000>;
60			fsl,num-laws = <8>;
61		};
62
63		ecm@1000 {
64			compatible = "fsl,mpc8555-ecm", "fsl,ecm";
65			reg = <0x1000 0x1000>;
66			interrupts = <17 2>;
67			interrupt-parent = <&mpic>;
68		};
69
70		memory-controller@2000 {
71			compatible = "fsl,mpc8555-memory-controller";
72			reg = <0x2000 0x1000>;
73			interrupt-parent = <&mpic>;
74			interrupts = <18 2>;
75		};
76
77		L2: l2-cache-controller@20000 {
78			compatible = "fsl,mpc8555-l2-cache-controller";
79			reg = <0x20000 0x1000>;
80			cache-line-size = <32>;	// 32 bytes
81			cache-size = <0x40000>;	// L2, 256K
82			interrupt-parent = <&mpic>;
83			interrupts = <16 2>;
84		};
85
86		i2c@3000 {
87			#address-cells = <1>;
88			#size-cells = <0>;
89			cell-index = <0>;
90			compatible = "fsl-i2c";
91			reg = <0x3000 0x100>;
92			interrupts = <43 2>;
93			interrupt-parent = <&mpic>;
94			dfsrr;
95		};
96
97		dma@21300 {
98			#address-cells = <1>;
99			#size-cells = <1>;
100			compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
101			reg = <0x21300 0x4>;
102			ranges = <0x0 0x21100 0x200>;
103			cell-index = <0>;
104			dma-channel@0 {
105				compatible = "fsl,mpc8555-dma-channel",
106						"fsl,eloplus-dma-channel";
107				reg = <0x0 0x80>;
108				cell-index = <0>;
109				interrupt-parent = <&mpic>;
110				interrupts = <20 2>;
111			};
112			dma-channel@80 {
113				compatible = "fsl,mpc8555-dma-channel",
114						"fsl,eloplus-dma-channel";
115				reg = <0x80 0x80>;
116				cell-index = <1>;
117				interrupt-parent = <&mpic>;
118				interrupts = <21 2>;
119			};
120			dma-channel@100 {
121				compatible = "fsl,mpc8555-dma-channel",
122						"fsl,eloplus-dma-channel";
123				reg = <0x100 0x80>;
124				cell-index = <2>;
125				interrupt-parent = <&mpic>;
126				interrupts = <22 2>;
127			};
128			dma-channel@180 {
129				compatible = "fsl,mpc8555-dma-channel",
130						"fsl,eloplus-dma-channel";
131				reg = <0x180 0x80>;
132				cell-index = <3>;
133				interrupt-parent = <&mpic>;
134				interrupts = <23 2>;
135			};
136		};
137
138		enet0: ethernet@24000 {
139			#address-cells = <1>;
140			#size-cells = <1>;
141			cell-index = <0>;
142			device_type = "network";
143			model = "TSEC";
144			compatible = "gianfar";
145			reg = <0x24000 0x1000>;
146			ranges = <0x0 0x24000 0x1000>;
147			local-mac-address = [ 00 00 00 00 00 00 ];
148			interrupts = <29 2 30 2 34 2>;
149			interrupt-parent = <&mpic>;
150			tbi-handle = <&tbi0>;
151			phy-handle = <&phy0>;
152
153			mdio@520 {
154				#address-cells = <1>;
155				#size-cells = <0>;
156				compatible = "fsl,gianfar-mdio";
157				reg = <0x520 0x20>;
158
159				phy0: ethernet-phy@2 {
160					interrupt-parent = <&mpic>;
161					interrupts = <5 1>;
162					reg = <0x2>;
163				};
164				phy1: ethernet-phy@4 {
165					interrupt-parent = <&mpic>;
166					interrupts = <5 1>;
167					reg = <0x4>;
168				};
169				tbi0: tbi-phy@11 {
170					reg = <0x11>;
171					device_type = "tbi-phy";
172				};
173			};
174		};
175
176		enet1: ethernet@25000 {
177			#address-cells = <1>;
178			#size-cells = <1>;
179			cell-index = <1>;
180			device_type = "network";
181			model = "TSEC";
182			compatible = "gianfar";
183			reg = <0x25000 0x1000>;
184			ranges = <0x0 0x25000 0x1000>;
185			local-mac-address = [ 00 00 00 00 00 00 ];
186			interrupts = <35 2 36 2 40 2>;
187			interrupt-parent = <&mpic>;
188			tbi-handle = <&tbi1>;
189			phy-handle = <&phy1>;
190
191			mdio@520 {
192				#address-cells = <1>;
193				#size-cells = <0>;
194				compatible = "fsl,gianfar-tbi";
195				reg = <0x520 0x20>;
196
197				tbi1: tbi-phy@11 {
198					reg = <0x11>;
199					device_type = "tbi-phy";
200				};
201			};
202		};
203
204		serial0: serial@4500 {
205			cell-index = <0>;
206			device_type = "serial";
207			compatible = "fsl,ns16550", "ns16550";
208			reg = <0x4500 0x100>; 	// reg base, size
209			clock-frequency = <0>; 	// should we fill in in uboot?
210			interrupts = <42 2>;
211			interrupt-parent = <&mpic>;
212		};
213
214		serial1: serial@4600 {
215			cell-index = <1>;
216			device_type = "serial";
217			compatible = "fsl,ns16550", "ns16550";
218			reg = <0x4600 0x100>;	// reg base, size
219			clock-frequency = <0>; 	// should we fill in in uboot?
220			interrupts = <42 2>;
221			interrupt-parent = <&mpic>;
222		};
223
224		crypto@30000 {
225			compatible = "fsl,sec2.0";
226			reg = <0x30000 0x10000>;
227			interrupts = <45 2>;
228			interrupt-parent = <&mpic>;
229			fsl,num-channels = <4>;
230			fsl,channel-fifo-len = <24>;
231			fsl,exec-units-mask = <0x7e>;
232			fsl,descriptor-types-mask = <0x01010ebf>;
233		};
234
235		mpic: pic@40000 {
236			interrupt-controller;
237			#address-cells = <0>;
238			#interrupt-cells = <2>;
239			reg = <0x40000 0x40000>;
240			compatible = "chrp,open-pic";
241			device_type = "open-pic";
242		};
243
244		cpm@919c0 {
245			#address-cells = <1>;
246			#size-cells = <1>;
247			compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
248			reg = <0x919c0 0x30>;
249			ranges;
250
251			muram@80000 {
252				#address-cells = <1>;
253				#size-cells = <1>;
254				ranges = <0x0 0x80000 0x10000>;
255
256				data@0 {
257					compatible = "fsl,cpm-muram-data";
258					reg = <0x0 0x2000 0x9000 0x1000>;
259				};
260			};
261
262			brg@919f0 {
263				compatible = "fsl,mpc8555-brg",
264				             "fsl,cpm2-brg",
265				             "fsl,cpm-brg";
266				reg = <0x919f0 0x10 0x915f0 0x10>;
267			};
268
269			cpmpic: pic@90c00 {
270				interrupt-controller;
271				#address-cells = <0>;
272				#interrupt-cells = <2>;
273				interrupts = <46 2>;
274				interrupt-parent = <&mpic>;
275				reg = <0x90c00 0x80>;
276				compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
277			};
278		};
279	};
280
281	pci0: pci@e0008000 {
282		interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
283		interrupt-map = <
284
285			/* IDSEL 0x10 */
286			0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
287			0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
288			0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
289			0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
290
291			/* IDSEL 0x11 */
292			0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
293			0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
294			0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
295			0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
296
297			/* IDSEL 0x12 (Slot 1) */
298			0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
299			0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
300			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
301			0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
302
303			/* IDSEL 0x13 (Slot 2) */
304			0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
305			0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
306			0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
307			0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
308
309			/* IDSEL 0x14 (Slot 3) */
310			0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
311			0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
312			0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
313			0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
314
315			/* IDSEL 0x15 (Slot 4) */
316			0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
317			0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
318			0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
319			0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
320
321			/* Bus 1 (Tundra Bridge) */
322			/* IDSEL 0x12 (ISA bridge) */
323			0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
324			0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
325			0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
326			0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
327		interrupt-parent = <&mpic>;
328		interrupts = <24 2>;
329		bus-range = <0 0>;
330		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
331			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
332		clock-frequency = <66666666>;
333		#interrupt-cells = <1>;
334		#size-cells = <2>;
335		#address-cells = <3>;
336		reg = <0xe0008000 0x1000>;
337		compatible = "fsl,mpc8540-pci";
338		device_type = "pci";
339
340		i8259@19000 {
341			interrupt-controller;
342			device_type = "interrupt-controller";
343			reg = <0x19000 0x0 0x0 0x0 0x1>;
344			#address-cells = <0>;
345			#interrupt-cells = <2>;
346			compatible = "chrp,iic";
347			interrupts = <1>;
348			interrupt-parent = <&pci0>;
349		};
350	};
351
352	pci1: pci@e0009000 {
353		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
354		interrupt-map = <
355
356			/* IDSEL 0x15 */
357			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
358			0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
359			0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
360			0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
361		interrupt-parent = <&mpic>;
362		interrupts = <25 2>;
363		bus-range = <0 0>;
364		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
365			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
366		clock-frequency = <66666666>;
367		#interrupt-cells = <1>;
368		#size-cells = <2>;
369		#address-cells = <3>;
370		reg = <0xe0009000 0x1000>;
371		compatible = "fsl,mpc8540-pci";
372		device_type = "pci";
373	};
374};
375