1/*
2 * MPC8555-based STx GP3 Device Tree Source
3 *
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 *
6 * Copyright 2010 Silicon Turnkey Express LLC.
7 *
8 * This program is free software; you can redistribute  it and/or modify it
9 * under  the terms of  the GNU General  Public License as published by the
10 * Free Software Foundation;  either version 2 of the  License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17	model = "stx,gp3";
18        compatible = "stx,gp3-8560", "stx,gp3";
19	#address-cells = <1>;
20	#size-cells = <1>;
21
22	aliases {
23		ethernet0 = &enet0;
24		ethernet1 = &enet1;
25		serial0 = &serial0;
26		serial1 = &serial1;
27		pci0 = &pci0;
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		PowerPC,8555@0 {
35			device_type = "cpu";
36			reg = <0x0>;
37			d-cache-line-size = <32>;	// 32 bytes
38			i-cache-line-size = <32>;	// 32 bytes
39			d-cache-size = <0x8000>;		// L1, 32K
40			i-cache-size = <0x8000>;		// L1, 32K
41			timebase-frequency = <0>;	//  33 MHz, from uboot
42			bus-frequency = <0>;	// 166 MHz
43			clock-frequency = <0>;	// 825 MHz, from uboot
44			next-level-cache = <&L2>;
45		};
46	};
47
48	memory {
49		device_type = "memory";
50		reg = <0x00000000 0x10000000>;
51	};
52
53	soc8555@e0000000 {
54		#address-cells = <1>;
55		#size-cells = <1>;
56		device_type = "soc";
57		compatible = "simple-bus";
58		ranges = <0x0 0xe0000000 0x100000>;
59		bus-frequency = <0>;
60
61		ecm-law@0 {
62			compatible = "fsl,ecm-law";
63			reg = <0x0 0x1000>;
64			fsl,num-laws = <8>;
65		};
66
67		ecm@1000 {
68			compatible = "fsl,mpc8555-ecm", "fsl,ecm";
69			reg = <0x1000 0x1000>;
70			interrupts = <17 2>;
71			interrupt-parent = <&mpic>;
72		};
73
74		memory-controller@2000 {
75			compatible = "fsl,mpc8555-memory-controller";
76			reg = <0x2000 0x1000>;
77			interrupt-parent = <&mpic>;
78			interrupts = <18 2>;
79		};
80
81		L2: l2-cache-controller@20000 {
82			compatible = "fsl,mpc8555-l2-cache-controller";
83			reg = <0x20000 0x1000>;
84			cache-line-size = <32>;	// 32 bytes
85			cache-size = <0x40000>;	// L2, 256K
86			interrupt-parent = <&mpic>;
87			interrupts = <16 2>;
88		};
89
90		i2c@3000 {
91			#address-cells = <1>;
92			#size-cells = <0>;
93			cell-index = <0>;
94			compatible = "fsl-i2c";
95			reg = <0x3000 0x100>;
96			interrupts = <43 2>;
97			interrupt-parent = <&mpic>;
98			dfsrr;
99		};
100
101		dma@21300 {
102			#address-cells = <1>;
103			#size-cells = <1>;
104			compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
105			reg = <0x21300 0x4>;
106			ranges = <0x0 0x21100 0x200>;
107			cell-index = <0>;
108			dma-channel@0 {
109				compatible = "fsl,mpc8555-dma-channel",
110						"fsl,eloplus-dma-channel";
111				reg = <0x0 0x80>;
112				cell-index = <0>;
113				interrupt-parent = <&mpic>;
114				interrupts = <20 2>;
115			};
116			dma-channel@80 {
117				compatible = "fsl,mpc8555-dma-channel",
118						"fsl,eloplus-dma-channel";
119				reg = <0x80 0x80>;
120				cell-index = <1>;
121				interrupt-parent = <&mpic>;
122				interrupts = <21 2>;
123			};
124			dma-channel@100 {
125				compatible = "fsl,mpc8555-dma-channel",
126						"fsl,eloplus-dma-channel";
127				reg = <0x100 0x80>;
128				cell-index = <2>;
129				interrupt-parent = <&mpic>;
130				interrupts = <22 2>;
131			};
132			dma-channel@180 {
133				compatible = "fsl,mpc8555-dma-channel",
134						"fsl,eloplus-dma-channel";
135				reg = <0x180 0x80>;
136				cell-index = <3>;
137				interrupt-parent = <&mpic>;
138				interrupts = <23 2>;
139			};
140		};
141
142		enet0: ethernet@24000 {
143			#address-cells = <1>;
144			#size-cells = <1>;
145			cell-index = <0>;
146			device_type = "network";
147			model = "TSEC";
148			compatible = "gianfar";
149			reg = <0x24000 0x1000>;
150			ranges = <0x0 0x24000 0x1000>;
151			local-mac-address = [ 00 00 00 00 00 00 ];
152			interrupts = <29 2 30 2 34 2>;
153			interrupt-parent = <&mpic>;
154			tbi-handle = <&tbi0>;
155			phy-handle = <&phy0>;
156
157			mdio@520 {
158				#address-cells = <1>;
159				#size-cells = <0>;
160				compatible = "fsl,gianfar-mdio";
161				reg = <0x520 0x20>;
162
163				phy0: ethernet-phy@2 {
164					interrupt-parent = <&mpic>;
165					interrupts = <5 1>;
166					reg = <0x2>;
167				};
168				phy1: ethernet-phy@4 {
169					interrupt-parent = <&mpic>;
170					interrupts = <5 1>;
171					reg = <0x4>;
172				};
173				tbi0: tbi-phy@11 {
174					reg = <0x11>;
175					device_type = "tbi-phy";
176				};
177			};
178		};
179
180		enet1: ethernet@25000 {
181			#address-cells = <1>;
182			#size-cells = <1>;
183			cell-index = <1>;
184			device_type = "network";
185			model = "TSEC";
186			compatible = "gianfar";
187			reg = <0x25000 0x1000>;
188			ranges = <0x0 0x25000 0x1000>;
189			local-mac-address = [ 00 00 00 00 00 00 ];
190			interrupts = <35 2 36 2 40 2>;
191			interrupt-parent = <&mpic>;
192			tbi-handle = <&tbi1>;
193			phy-handle = <&phy1>;
194
195			mdio@520 {
196				#address-cells = <1>;
197				#size-cells = <0>;
198				compatible = "fsl,gianfar-tbi";
199				reg = <0x520 0x20>;
200
201				tbi1: tbi-phy@11 {
202					reg = <0x11>;
203					device_type = "tbi-phy";
204				};
205			};
206		};
207
208		serial0: serial@4500 {
209			cell-index = <0>;
210			device_type = "serial";
211			compatible = "fsl,ns16550", "ns16550";
212			reg = <0x4500 0x100>; 	// reg base, size
213			clock-frequency = <0>; 	// should we fill in in uboot?
214			interrupts = <42 2>;
215			interrupt-parent = <&mpic>;
216		};
217
218		serial1: serial@4600 {
219			cell-index = <1>;
220			device_type = "serial";
221			compatible = "fsl,ns16550", "ns16550";
222			reg = <0x4600 0x100>;	// reg base, size
223			clock-frequency = <0>; 	// should we fill in in uboot?
224			interrupts = <42 2>;
225			interrupt-parent = <&mpic>;
226		};
227
228		crypto@30000 {
229			compatible = "fsl,sec2.0";
230			reg = <0x30000 0x10000>;
231			interrupts = <45 2>;
232			interrupt-parent = <&mpic>;
233			fsl,num-channels = <4>;
234			fsl,channel-fifo-len = <24>;
235			fsl,exec-units-mask = <0x7e>;
236			fsl,descriptor-types-mask = <0x01010ebf>;
237		};
238
239		mpic: pic@40000 {
240			interrupt-controller;
241			#address-cells = <0>;
242			#interrupt-cells = <2>;
243			reg = <0x40000 0x40000>;
244			compatible = "chrp,open-pic";
245			device_type = "open-pic";
246		};
247
248		cpm@919c0 {
249			#address-cells = <1>;
250			#size-cells = <1>;
251			compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
252			reg = <0x919c0 0x30>;
253			ranges;
254
255			muram@80000 {
256				#address-cells = <1>;
257				#size-cells = <1>;
258				ranges = <0x0 0x80000 0x10000>;
259
260				data@0 {
261					compatible = "fsl,cpm-muram-data";
262					reg = <0x0 0x2000 0x9000 0x1000>;
263				};
264			};
265
266			brg@919f0 {
267				compatible = "fsl,mpc8555-brg",
268				             "fsl,cpm2-brg",
269				             "fsl,cpm-brg";
270				reg = <0x919f0 0x10 0x915f0 0x10>;
271			};
272
273			cpmpic: pic@90c00 {
274				interrupt-controller;
275				#address-cells = <0>;
276				#interrupt-cells = <2>;
277				interrupts = <46 2>;
278				interrupt-parent = <&mpic>;
279				reg = <0x90c00 0x80>;
280				compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
281			};
282		};
283	};
284
285	pci0: pci@e0008000 {
286		interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
287		interrupt-map = <
288
289			/* IDSEL 0x10 */
290			0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
291			0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
292			0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
293			0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
294
295			/* IDSEL 0x11 */
296			0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
297			0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
298			0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
299			0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
300
301			/* IDSEL 0x12 (Slot 1) */
302			0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
303			0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
304			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
305			0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
306
307			/* IDSEL 0x13 (Slot 2) */
308			0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
309			0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
310			0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
311			0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
312
313			/* IDSEL 0x14 (Slot 3) */
314			0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
315			0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
316			0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
317			0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
318
319			/* IDSEL 0x15 (Slot 4) */
320			0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
321			0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
322			0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
323			0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
324
325			/* Bus 1 (Tundra Bridge) */
326			/* IDSEL 0x12 (ISA bridge) */
327			0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
328			0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
329			0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
330			0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
331		interrupt-parent = <&mpic>;
332		interrupts = <24 2>;
333		bus-range = <0 0>;
334		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
335			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
336		clock-frequency = <66666666>;
337		#interrupt-cells = <1>;
338		#size-cells = <2>;
339		#address-cells = <3>;
340		reg = <0xe0008000 0x1000>;
341		compatible = "fsl,mpc8540-pci";
342		device_type = "pci";
343
344		i8259@19000 {
345			interrupt-controller;
346			device_type = "interrupt-controller";
347			reg = <0x19000 0x0 0x0 0x0 0x1>;
348			#address-cells = <0>;
349			#interrupt-cells = <2>;
350			compatible = "chrp,iic";
351			interrupts = <1>;
352			interrupt-parent = <&pci0>;
353		};
354	};
355
356	pci1: pci@e0009000 {
357		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
358		interrupt-map = <
359
360			/* IDSEL 0x15 */
361			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
362			0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
363			0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
364			0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
365		interrupt-parent = <&mpic>;
366		interrupts = <25 2>;
367		bus-range = <0 0>;
368		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
369			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
370		clock-frequency = <66666666>;
371		#interrupt-cells = <1>;
372		#size-cells = <2>;
373		#address-cells = <3>;
374		reg = <0xe0009000 0x1000>;
375		compatible = "fsl,mpc8540-pci";
376		device_type = "pci";
377	};
378};
379