1/*
2 * STX GP3 - 8560 ADS Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "stx,gp3";
16	compatible = "stx,gp3-8560", "stx,gp3";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		pci0 = &pci0;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		PowerPC,8560@0 {
32			device_type = "cpu";
33			reg = <0>;
34			d-cache-line-size = <32>;
35			i-cache-line-size = <32>;
36			d-cache-size = <32768>;
37			i-cache-size = <32768>;
38			timebase-frequency = <0>;
39			bus-frequency = <0>;
40			clock-frequency = <0>;
41			next-level-cache = <&L2>;
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x00000000 0x10000000>;
48	};
49
50	soc@fdf00000 {
51		#address-cells = <1>;
52		#size-cells = <1>;
53		device_type = "soc";
54		ranges = <0 0xfdf00000 0x100000>;
55		reg = <0xfdf00000 0x1000>;
56		bus-frequency = <0>;
57		compatible = "fsl,mpc8560-immr", "simple-bus";
58
59		ecm-law@0 {
60			compatible = "fsl,ecm-law";
61			reg = <0x0 0x1000>;
62			fsl,num-laws = <8>;
63		};
64
65		ecm@1000 {
66			compatible = "fsl,mpc8560-ecm", "fsl,ecm";
67			reg = <0x1000 0x1000>;
68			interrupts = <17 2>;
69			interrupt-parent = <&mpic>;
70		};
71
72		memory-controller@2000 {
73			compatible = "fsl,mpc8540-memory-controller";
74			reg = <0x2000 0x1000>;
75			interrupt-parent = <&mpic>;
76			interrupts = <18 2>;
77		};
78
79		L2: l2-cache-controller@20000 {
80			compatible = "fsl,mpc8540-l2-cache-controller";
81			reg = <0x20000 0x1000>;
82			cache-line-size = <32>;
83			cache-size = <0x40000>;	// L2, 256K
84			interrupt-parent = <&mpic>;
85			interrupts = <16 2>;
86		};
87
88		i2c@3000 {
89			#address-cells = <1>;
90			#size-cells = <0>;
91			cell-index = <0>;
92			compatible = "fsl-i2c";
93			reg = <0x3000 0x100>;
94			interrupts = <43 2>;
95			interrupt-parent = <&mpic>;
96			dfsrr;
97		};
98
99		dma@21300 {
100			#address-cells = <1>;
101			#size-cells = <1>;
102			compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
103			reg = <0x21300 0x4>;
104			ranges = <0x0 0x21100 0x200>;
105			cell-index = <0>;
106			dma-channel@0 {
107				compatible = "fsl,mpc8560-dma-channel",
108						"fsl,eloplus-dma-channel";
109				reg = <0x0 0x80>;
110				cell-index = <0>;
111				interrupt-parent = <&mpic>;
112				interrupts = <20 2>;
113			};
114			dma-channel@80 {
115				compatible = "fsl,mpc8560-dma-channel",
116						"fsl,eloplus-dma-channel";
117				reg = <0x80 0x80>;
118				cell-index = <1>;
119				interrupt-parent = <&mpic>;
120				interrupts = <21 2>;
121			};
122			dma-channel@100 {
123				compatible = "fsl,mpc8560-dma-channel",
124						"fsl,eloplus-dma-channel";
125				reg = <0x100 0x80>;
126				cell-index = <2>;
127				interrupt-parent = <&mpic>;
128				interrupts = <22 2>;
129			};
130			dma-channel@180 {
131				compatible = "fsl,mpc8560-dma-channel",
132						"fsl,eloplus-dma-channel";
133				reg = <0x180 0x80>;
134				cell-index = <3>;
135				interrupt-parent = <&mpic>;
136				interrupts = <23 2>;
137			};
138		};
139
140		enet0: ethernet@24000 {
141			#address-cells = <1>;
142			#size-cells = <1>;
143			cell-index = <0>;
144			device_type = "network";
145			model = "TSEC";
146			compatible = "gianfar";
147			reg = <0x24000 0x1000>;
148			ranges = <0x0 0x24000 0x1000>;
149			local-mac-address = [ 00 00 00 00 00 00 ];
150			interrupts = <29 2 30 2 34 2>;
151			interrupt-parent = <&mpic>;
152			tbi-handle = <&tbi0>;
153			phy-handle = <&phy2>;
154
155			mdio@520 {
156				#address-cells = <1>;
157				#size-cells = <0>;
158				compatible = "fsl,gianfar-mdio";
159				reg = <0x520 0x20>;
160
161				phy2: ethernet-phy@2 {
162					interrupt-parent = <&mpic>;
163					interrupts = <5 4>;
164					reg = <2>;
165					device_type = "ethernet-phy";
166				};
167				phy4: ethernet-phy@4 {
168					interrupt-parent = <&mpic>;
169					interrupts = <5 4>;
170					reg = <4>;
171					device_type = "ethernet-phy";
172				};
173				tbi0: tbi-phy@11 {
174					reg = <0x11>;
175					device_type = "tbi-phy";
176				};
177			};
178		};
179
180		enet1: ethernet@25000 {
181			#address-cells = <1>;
182			#size-cells = <1>;
183			cell-index = <1>;
184			device_type = "network";
185			model = "TSEC";
186			compatible = "gianfar";
187			reg = <0x25000 0x1000>;
188			ranges = <0x0 0x25000 0x1000>;
189			local-mac-address = [ 00 00 00 00 00 00 ];
190			interrupts = <35 2 36 2 40 2>;
191			interrupt-parent = <&mpic>;
192			tbi-handle = <&tbi1>;
193			phy-handle = <&phy4>;
194
195			mdio@520 {
196				#address-cells = <1>;
197				#size-cells = <0>;
198				compatible = "fsl,gianfar-tbi";
199				reg = <0x520 0x20>;
200
201				tbi1: tbi-phy@11 {
202					reg = <0x11>;
203					device_type = "tbi-phy";
204				};
205			};
206		};
207
208		mpic: pic@40000 {
209			interrupt-controller;
210			#address-cells = <0>;
211			#interrupt-cells = <2>;
212			reg = <0x40000 0x40000>;
213			compatible = "chrp,open-pic";
214			device_type = "open-pic";
215		};
216
217		cpm@919c0 {
218			#address-cells = <1>;
219			#size-cells = <1>;
220			compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
221			reg = <0x919c0 0x30>;
222			ranges;
223
224			muram@80000 {
225				#address-cells = <1>;
226				#size-cells = <1>;
227				ranges = <0 0x80000 0x10000>;
228
229				data@0 {
230					compatible = "fsl,cpm-muram-data";
231					reg = <0 0x4000 0x9000 0x2000>;
232				};
233			};
234
235			brg@919f0 {
236				compatible = "fsl,mpc8560-brg",
237				             "fsl,cpm2-brg",
238				             "fsl,cpm-brg";
239				reg = <0x919f0 0x10 0x915f0 0x10>;
240				clock-frequency = <0>;
241			};
242
243			cpmpic: pic@90c00 {
244				interrupt-controller;
245				#address-cells = <0>;
246				#interrupt-cells = <2>;
247				interrupts = <46 2>;
248				interrupt-parent = <&mpic>;
249				reg = <0x90c00 0x80>;
250				compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
251			};
252
253			serial0: serial@91a20 {
254				device_type = "serial";
255				compatible = "fsl,mpc8560-scc-uart",
256				             "fsl,cpm2-scc-uart";
257				reg = <0x91a20 0x20 0x88100 0x100>;
258				fsl,cpm-brg = <2>;
259				fsl,cpm-command = <0x4a00000>;
260				interrupts = <41 8>;
261				interrupt-parent = <&cpmpic>;
262			};
263		};
264	};
265
266	pci0: pci@fdf08000 {
267		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
268		interrupt-map = <
269
270			/* IDSEL 0x0c */
271			0x6000 0 0 1 &mpic 1 1
272			0x6000 0 0 2 &mpic 2 1
273			0x6000 0 0 3 &mpic 3 1
274			0x6000 0 0 4 &mpic 4 1
275
276			/* IDSEL 0x0d */
277			0x6800 0 0 1 &mpic 4 1
278			0x6800 0 0 2 &mpic 1 1
279			0x6800 0 0 3 &mpic 2 1
280			0x6800 0 0 4 &mpic 3 1
281
282			/* IDSEL 0x0e */
283			0x7000 0 0 1 &mpic 3 1
284			0x7000 0 0 2 &mpic 4 1
285			0x7000 0 0 3 &mpic 1 1
286			0x7000 0 0 4 &mpic 2 1
287
288			/* IDSEL 0x0f */
289			0x7800 0 0 1 &mpic 2 1
290			0x7800 0 0 2 &mpic 3 1
291			0x7800 0 0 3 &mpic 4 1
292			0x7800 0 0 4 &mpic 1 1>;
293
294		interrupt-parent = <&mpic>;
295		interrupts = <24 2>;
296		bus-range = <0 0>;
297		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
298			  0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
299		clock-frequency = <66666666>;
300		#interrupt-cells = <1>;
301		#size-cells = <2>;
302		#address-cells = <3>;
303		reg = <0xfdf08000 0x1000>;
304		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
305		device_type = "pci";
306	};
307};
308