1/* 2 * STX GP3 - 8560 ADS Device Tree Source 3 * 4 * Copyright 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "stx,gp3"; 16 compatible = "stx,gp3-8560", "stx,gp3"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 pci0 = &pci0; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 PowerPC,8560@0 { 32 device_type = "cpu"; 33 reg = <0>; 34 d-cache-line-size = <32>; 35 i-cache-line-size = <32>; 36 d-cache-size = <32768>; 37 i-cache-size = <32768>; 38 timebase-frequency = <0>; 39 bus-frequency = <0>; 40 clock-frequency = <0>; 41 next-level-cache = <&L2>; 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <0x00000000 0x10000000>; 48 }; 49 50 soc@fdf00000 { 51 #address-cells = <1>; 52 #size-cells = <1>; 53 device_type = "soc"; 54 ranges = <0 0xfdf00000 0x100000>; 55 reg = <0xfdf00000 0x1000>; 56 bus-frequency = <0>; 57 compatible = "fsl,mpc8560-immr", "simple-bus"; 58 59 memory-controller@2000 { 60 compatible = "fsl,8540-memory-controller"; 61 reg = <0x2000 0x1000>; 62 interrupt-parent = <&mpic>; 63 interrupts = <18 2>; 64 }; 65 66 L2: l2-cache-controller@20000 { 67 compatible = "fsl,8540-l2-cache-controller"; 68 reg = <0x20000 0x1000>; 69 cache-line-size = <32>; 70 cache-size = <0x40000>; // L2, 256K 71 interrupt-parent = <&mpic>; 72 interrupts = <16 2>; 73 }; 74 75 i2c@3000 { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 cell-index = <0>; 79 compatible = "fsl-i2c"; 80 reg = <0x3000 0x100>; 81 interrupts = <43 2>; 82 interrupt-parent = <&mpic>; 83 dfsrr; 84 }; 85 86 mdio@24520 { 87 #address-cells = <1>; 88 #size-cells = <0>; 89 compatible = "fsl,gianfar-mdio"; 90 reg = <0x24520 0x20>; 91 92 phy2: ethernet-phy@2 { 93 interrupt-parent = <&mpic>; 94 interrupts = <5 4>; 95 reg = <2>; 96 device_type = "ethernet-phy"; 97 }; 98 phy4: ethernet-phy@4 { 99 interrupt-parent = <&mpic>; 100 interrupts = <5 4>; 101 reg = <4>; 102 device_type = "ethernet-phy"; 103 }; 104 }; 105 106 enet0: ethernet@24000 { 107 cell-index = <0>; 108 device_type = "network"; 109 model = "TSEC"; 110 compatible = "gianfar"; 111 reg = <0x24000 0x1000>; 112 local-mac-address = [ 00 00 00 00 00 00 ]; 113 interrupts = <29 2 30 2 34 2>; 114 interrupt-parent = <&mpic>; 115 phy-handle = <&phy2>; 116 }; 117 118 enet1: ethernet@25000 { 119 cell-index = <1>; 120 device_type = "network"; 121 model = "TSEC"; 122 compatible = "gianfar"; 123 reg = <0x25000 0x1000>; 124 local-mac-address = [ 00 00 00 00 00 00 ]; 125 interrupts = <35 2 36 2 40 2>; 126 interrupt-parent = <&mpic>; 127 phy-handle = <&phy4>; 128 }; 129 130 mpic: pic@40000 { 131 interrupt-controller; 132 #address-cells = <0>; 133 #interrupt-cells = <2>; 134 reg = <0x40000 0x40000>; 135 compatible = "chrp,open-pic"; 136 device_type = "open-pic"; 137 }; 138 139 cpm@919c0 { 140 #address-cells = <1>; 141 #size-cells = <1>; 142 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus"; 143 reg = <0x919c0 0x30>; 144 ranges; 145 146 muram@80000 { 147 #address-cells = <1>; 148 #size-cells = <1>; 149 ranges = <0 0x80000 0x10000>; 150 151 data@0 { 152 compatible = "fsl,cpm-muram-data"; 153 reg = <0 0x4000 0x9000 0x2000>; 154 }; 155 }; 156 157 brg@919f0 { 158 compatible = "fsl,mpc8560-brg", 159 "fsl,cpm2-brg", 160 "fsl,cpm-brg"; 161 reg = <0x919f0 0x10 0x915f0 0x10>; 162 clock-frequency = <0>; 163 }; 164 165 cpmpic: pic@90c00 { 166 interrupt-controller; 167 #address-cells = <0>; 168 #interrupt-cells = <2>; 169 interrupts = <46 2>; 170 interrupt-parent = <&mpic>; 171 reg = <0x90c00 0x80>; 172 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; 173 }; 174 175 serial0: serial@91a20 { 176 device_type = "serial"; 177 compatible = "fsl,mpc8560-scc-uart", 178 "fsl,cpm2-scc-uart"; 179 reg = <0x91a20 0x20 0x88100 0x100>; 180 fsl,cpm-brg = <2>; 181 fsl,cpm-command = <0x4a00000>; 182 interrupts = <41 8>; 183 interrupt-parent = <&cpmpic>; 184 }; 185 }; 186 }; 187 188 pci0: pci@fdf08000 { 189 cell-index = <0>; 190 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 191 interrupt-map = < 192 193 /* IDSEL 0x0c */ 194 0x6000 0 0 1 &mpic 1 1 195 0x6000 0 0 2 &mpic 2 1 196 0x6000 0 0 3 &mpic 3 1 197 0x6000 0 0 4 &mpic 4 1 198 199 /* IDSEL 0x0d */ 200 0x6800 0 0 1 &mpic 4 1 201 0x6800 0 0 2 &mpic 1 1 202 0x6800 0 0 3 &mpic 2 1 203 0x6800 0 0 4 &mpic 3 1 204 205 /* IDSEL 0x0e */ 206 0x7000 0 0 1 &mpic 3 1 207 0x7000 0 0 2 &mpic 4 1 208 0x7000 0 0 3 &mpic 1 1 209 0x7000 0 0 4 &mpic 2 1 210 211 /* IDSEL 0x0f */ 212 0x7800 0 0 1 &mpic 2 1 213 0x7800 0 0 2 &mpic 3 1 214 0x7800 0 0 3 &mpic 4 1 215 0x7800 0 0 4 &mpic 1 1>; 216 217 interrupt-parent = <&mpic>; 218 interrupts = <24 2>; 219 bus-range = <0 0>; 220 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 221 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; 222 clock-frequency = <66666666>; 223 #interrupt-cells = <1>; 224 #size-cells = <2>; 225 #address-cells = <3>; 226 reg = <0xfdf08000 0x1000>; 227 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 228 device_type = "pci"; 229 }; 230}; 231