1/*
2 * STX GP3 - 8560 ADS Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "stx,gp3";
16	compatible = "stx,gp3-8560", "stx,gp3";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		pci0 = &pci0;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		PowerPC,8560@0 {
32			device_type = "cpu";
33			reg = <0>;
34			d-cache-line-size = <32>;
35			i-cache-line-size = <32>;
36			d-cache-size = <32768>;
37			i-cache-size = <32768>;
38			timebase-frequency = <0>;
39			bus-frequency = <0>;
40			clock-frequency = <0>;
41		};
42	};
43
44	memory {
45		device_type = "memory";
46		reg = <0x00000000 0x10000000>;
47	};
48
49	soc@fdf00000 {
50		#address-cells = <1>;
51		#size-cells = <1>;
52		device_type = "soc";
53		ranges = <0 0xfdf00000 0x100000>;
54		reg = <0xfdf00000 0x1000>;
55		bus-frequency = <0>;
56		compatible = "fsl,mpc8560-immr", "simple-bus";
57
58		memory-controller@2000 {
59			compatible = "fsl,8540-memory-controller";
60			reg = <0x2000 0x1000>;
61			interrupt-parent = <&mpic>;
62			interrupts = <18 2>;
63		};
64
65		l2-cache-controller@20000 {
66			compatible = "fsl,8540-l2-cache-controller";
67			reg = <0x20000 0x1000>;
68			cache-line-size = <32>;
69			cache-size = <0x40000>;	// L2, 256K
70			interrupt-parent = <&mpic>;
71			interrupts = <16 2>;
72		};
73
74		i2c@3000 {
75			#address-cells = <1>;
76			#size-cells = <0>;
77			cell-index = <0>;
78			compatible = "fsl-i2c";
79			reg = <0x3000 0x100>;
80			interrupts = <43 2>;
81			interrupt-parent = <&mpic>;
82			dfsrr;
83		};
84
85		mdio@24520 {
86			#address-cells = <1>;
87			#size-cells = <0>;
88			compatible = "fsl,gianfar-mdio";
89			reg = <0x24520 0x20>;
90
91			phy2: ethernet-phy@2 {
92				interrupt-parent = <&mpic>;
93				interrupts = <5 4>;
94				reg = <2>;
95				device_type = "ethernet-phy";
96			};
97			phy4: ethernet-phy@4 {
98				interrupt-parent = <&mpic>;
99				interrupts = <5 4>;
100				reg = <4>;
101				device_type = "ethernet-phy";
102			};
103		};
104
105		enet0: ethernet@24000 {
106			cell-index = <0>;
107			device_type = "network";
108			model = "TSEC";
109			compatible = "gianfar";
110			reg = <0x24000 0x1000>;
111			local-mac-address = [ 00 00 00 00 00 00 ];
112			interrupts = <29 2 30 2 34 2>;
113			interrupt-parent = <&mpic>;
114			phy-handle = <&phy2>;
115		};
116
117		enet1: ethernet@25000 {
118			cell-index = <1>;
119			device_type = "network";
120			model = "TSEC";
121			compatible = "gianfar";
122			reg = <0x25000 0x1000>;
123			local-mac-address = [ 00 00 00 00 00 00 ];
124			interrupts = <35 2 36 2 40 2>;
125			interrupt-parent = <&mpic>;
126			phy-handle = <&phy4>;
127		};
128
129		mpic: pic@40000 {
130			interrupt-controller;
131			#address-cells = <0>;
132			#interrupt-cells = <2>;
133			reg = <0x40000 0x40000>;
134			device_type = "open-pic";
135		};
136
137		cpm@919c0 {
138			#address-cells = <1>;
139			#size-cells = <1>;
140			compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
141			reg = <0x919c0 0x30>;
142			ranges;
143
144			muram@80000 {
145				#address-cells = <1>;
146				#size-cells = <1>;
147				ranges = <0 0x80000 0x10000>;
148
149				data@0 {
150					compatible = "fsl,cpm-muram-data";
151					reg = <0 0x4000 0x9000 0x2000>;
152				};
153			};
154
155			brg@919f0 {
156				compatible = "fsl,mpc8560-brg",
157				             "fsl,cpm2-brg",
158				             "fsl,cpm-brg";
159				reg = <0x919f0 0x10 0x915f0 0x10>;
160				clock-frequency = <0>;
161			};
162
163			cpmpic: pic@90c00 {
164				interrupt-controller;
165				#address-cells = <0>;
166				#interrupt-cells = <2>;
167				interrupts = <46 2>;
168				interrupt-parent = <&mpic>;
169				reg = <0x90c00 0x80>;
170				compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
171			};
172
173			serial0: serial@91a20 {
174				device_type = "serial";
175				compatible = "fsl,mpc8560-scc-uart",
176				             "fsl,cpm2-scc-uart";
177				reg = <0x91a20 0x20 0x88100 0x100>;
178				fsl,cpm-brg = <2>;
179				fsl,cpm-command = <0x4a00000>;
180				interrupts = <41 8>;
181				interrupt-parent = <&cpmpic>;
182			};
183		};
184	};
185
186	pci0: pci@fdf08000 {
187		cell-index = <0>;
188		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
189		interrupt-map = <
190
191			/* IDSEL 0x0c */
192			0x6000 0 0 1 &mpic 1 1
193			0x6000 0 0 2 &mpic 2 1
194			0x6000 0 0 3 &mpic 3 1
195			0x6000 0 0 4 &mpic 4 1
196
197			/* IDSEL 0x0d */
198			0x6800 0 0 1 &mpic 4 1
199			0x6800 0 0 2 &mpic 1 1
200			0x6800 0 0 3 &mpic 2 1
201			0x6800 0 0 4 &mpic 3 1
202
203			/* IDSEL 0x0e */
204			0x7000 0 0 1 &mpic 3 1
205			0x7000 0 0 2 &mpic 4 1
206			0x7000 0 0 3 &mpic 1 1
207			0x7000 0 0 4 &mpic 2 1
208
209			/* IDSEL 0x0f */
210			0x7800 0 0 1 &mpic 2 1
211			0x7800 0 0 2 &mpic 3 1
212			0x7800 0 0 3 &mpic 4 1
213			0x7800 0 0 4 &mpic 1 1>;
214
215		interrupt-parent = <&mpic>;
216		interrupts = <24 2>;
217		bus-range = <0 0>;
218		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
219			  0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
220		clock-frequency = <66666666>;
221		#interrupt-cells = <1>;
222		#size-cells = <2>;
223		#address-cells = <3>;
224		reg = <0xfdf08000 0x1000>;
225		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
226		device_type = "pci";
227	};
228};
229