1/* 2 * Device Tree Source for the Socrates board (MPC8544). 3 * 4 * Copyright (c) 2008 Emcraft Systems. 5 * Sergei Poselenov, <sposelenov@emcraft.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/dts-v1/; 14 15/ { 16 model = "abb,socrates"; 17 compatible = "abb,socrates"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 aliases { 22 ethernet0 = &enet0; 23 ethernet1 = &enet1; 24 serial0 = &serial0; 25 serial1 = &serial1; 26 pci0 = &pci0; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 PowerPC,8544@0 { 34 device_type = "cpu"; 35 reg = <0>; 36 d-cache-line-size = <32>; 37 i-cache-line-size = <32>; 38 d-cache-size = <0x8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K 40 timebase-frequency = <0>; 41 bus-frequency = <0>; 42 clock-frequency = <0>; 43 next-level-cache = <&L2>; 44 }; 45 }; 46 47 memory { 48 device_type = "memory"; 49 reg = <0x00000000 0x00000000>; // Filled in by U-Boot 50 }; 51 52 soc8544@e0000000 { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 device_type = "soc"; 56 57 ranges = <0x00000000 0xe0000000 0x00100000>; 58 reg = <0xe0000000 0x00001000>; // CCSRBAR 1M 59 bus-frequency = <0>; // Filled in by U-Boot 60 compatible = "fsl,mpc8544-immr", "simple-bus"; 61 62 ecm-law@0 { 63 compatible = "fsl,ecm-law"; 64 reg = <0x0 0x1000>; 65 fsl,num-laws = <10>; 66 }; 67 68 ecm@1000 { 69 compatible = "fsl,mpc8544-ecm", "fsl,ecm"; 70 reg = <0x1000 0x1000>; 71 interrupts = <17 2>; 72 interrupt-parent = <&mpic>; 73 }; 74 75 memory-controller@2000 { 76 compatible = "fsl,mpc8544-memory-controller"; 77 reg = <0x2000 0x1000>; 78 interrupt-parent = <&mpic>; 79 interrupts = <18 2>; 80 }; 81 82 L2: l2-cache-controller@20000 { 83 compatible = "fsl,mpc8544-l2-cache-controller"; 84 reg = <0x20000 0x1000>; 85 cache-line-size = <32>; 86 cache-size = <0x40000>; // L2, 256K 87 interrupt-parent = <&mpic>; 88 interrupts = <16 2>; 89 }; 90 91 i2c@3000 { 92 #address-cells = <1>; 93 #size-cells = <0>; 94 cell-index = <0>; 95 compatible = "fsl,mpc8544-i2c", "fsl-i2c"; 96 reg = <0x3000 0x100>; 97 interrupts = <43 2>; 98 interrupt-parent = <&mpic>; 99 fsl,preserve-clocking; 100 101 dtt@28 { 102 compatible = "winbond,w83782d"; 103 reg = <0x28>; 104 }; 105 rtc@32 { 106 compatible = "epson,rx8025"; 107 reg = <0x32>; 108 interrupts = <7 1>; 109 interrupt-parent = <&mpic>; 110 }; 111 dtt@4c { 112 compatible = "dallas,ds75"; 113 reg = <0x4c>; 114 }; 115 ts@4a { 116 compatible = "ti,tsc2003"; 117 reg = <0x4a>; 118 interrupt-parent = <&mpic>; 119 interrupts = <8 1>; 120 }; 121 }; 122 123 i2c@3100 { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 cell-index = <1>; 127 compatible = "fsl,mpc8544-i2c", "fsl-i2c"; 128 reg = <0x3100 0x100>; 129 interrupts = <43 2>; 130 interrupt-parent = <&mpic>; 131 fsl,preserve-clocking; 132 }; 133 134 enet0: ethernet@24000 { 135 #address-cells = <1>; 136 #size-cells = <1>; 137 cell-index = <0>; 138 device_type = "network"; 139 model = "eTSEC"; 140 compatible = "gianfar"; 141 reg = <0x24000 0x1000>; 142 ranges = <0x0 0x24000 0x1000>; 143 local-mac-address = [ 00 00 00 00 00 00 ]; 144 interrupts = <29 2 30 2 34 2>; 145 interrupt-parent = <&mpic>; 146 phy-handle = <&phy0>; 147 tbi-handle = <&tbi0>; 148 phy-connection-type = "rgmii-id"; 149 150 mdio@520 { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 compatible = "fsl,gianfar-mdio"; 154 reg = <0x520 0x20>; 155 156 phy0: ethernet-phy@0 { 157 interrupt-parent = <&mpic>; 158 interrupts = <0 1>; 159 reg = <0>; 160 }; 161 phy1: ethernet-phy@1 { 162 interrupt-parent = <&mpic>; 163 interrupts = <0 1>; 164 reg = <1>; 165 }; 166 tbi0: tbi-phy@11 { 167 reg = <0x11>; 168 }; 169 }; 170 }; 171 172 enet1: ethernet@26000 { 173 #address-cells = <1>; 174 #size-cells = <1>; 175 cell-index = <1>; 176 device_type = "network"; 177 model = "eTSEC"; 178 compatible = "gianfar"; 179 reg = <0x26000 0x1000>; 180 ranges = <0x0 0x26000 0x1000>; 181 local-mac-address = [ 00 00 00 00 00 00 ]; 182 interrupts = <31 2 32 2 33 2>; 183 interrupt-parent = <&mpic>; 184 phy-handle = <&phy1>; 185 tbi-handle = <&tbi1>; 186 phy-connection-type = "rgmii-id"; 187 188 mdio@520 { 189 #address-cells = <1>; 190 #size-cells = <0>; 191 compatible = "fsl,gianfar-tbi"; 192 reg = <0x520 0x20>; 193 194 tbi1: tbi-phy@11 { 195 reg = <0x11>; 196 }; 197 }; 198 }; 199 200 serial0: serial@4500 { 201 cell-index = <0>; 202 device_type = "serial"; 203 compatible = "ns16550"; 204 reg = <0x4500 0x100>; 205 clock-frequency = <0>; 206 interrupts = <42 2>; 207 interrupt-parent = <&mpic>; 208 }; 209 210 serial1: serial@4600 { 211 cell-index = <1>; 212 device_type = "serial"; 213 compatible = "ns16550"; 214 reg = <0x4600 0x100>; 215 clock-frequency = <0>; 216 interrupts = <42 2>; 217 interrupt-parent = <&mpic>; 218 }; 219 220 global-utilities@e0000 { //global utilities block 221 compatible = "fsl,mpc8548-guts"; 222 reg = <0xe0000 0x1000>; 223 fsl,has-rstcr; 224 }; 225 226 mpic: pic@40000 { 227 interrupt-controller; 228 #address-cells = <0>; 229 #interrupt-cells = <2>; 230 reg = <0x40000 0x40000>; 231 compatible = "chrp,open-pic"; 232 device_type = "open-pic"; 233 }; 234 }; 235 236 237 localbus { 238 compatible = "fsl,mpc8544-localbus", 239 "fsl,pq3-localbus", 240 "simple-bus"; 241 #address-cells = <2>; 242 #size-cells = <1>; 243 reg = <0xe0005000 0x40>; 244 245 ranges = <0 0 0xfc000000 0x04000000 246 2 0 0xc8000000 0x04000000 247 3 0 0xc0000000 0x00100000 248 >; /* Overwritten by U-Boot */ 249 250 nor_flash@0,0 { 251 compatible = "amd,s29gl256n", "cfi-flash"; 252 bank-width = <2>; 253 reg = <0x0 0x000000 0x4000000>; 254 #address-cells = <1>; 255 #size-cells = <1>; 256 partition@0 { 257 label = "kernel"; 258 reg = <0x0 0x1e0000>; 259 read-only; 260 }; 261 partition@1e0000 { 262 label = "dtb"; 263 reg = <0x1e0000 0x20000>; 264 }; 265 partition@200000 { 266 label = "root"; 267 reg = <0x200000 0x200000>; 268 }; 269 partition@400000 { 270 label = "user"; 271 reg = <0x400000 0x3b80000>; 272 }; 273 partition@3f80000 { 274 label = "env"; 275 reg = <0x3f80000 0x40000>; 276 read-only; 277 }; 278 partition@3fc0000 { 279 label = "u-boot"; 280 reg = <0x3fc0000 0x40000>; 281 read-only; 282 }; 283 }; 284 285 display@2,0 { 286 compatible = "fujitsu,lime"; 287 reg = <2 0x0 0x4000000>; 288 interrupt-parent = <&mpic>; 289 interrupts = <6 1>; 290 }; 291 292 fpga_pic: fpga-pic@3,10 { 293 compatible = "abb,socrates-fpga-pic"; 294 reg = <3 0x10 0x10>; 295 interrupt-controller; 296 /* IRQs 2, 10, 11, active low, level-sensitive */ 297 interrupts = <2 1 10 1 11 1>; 298 interrupt-parent = <&mpic>; 299 #interrupt-cells = <3>; 300 }; 301 302 spi@3,60 { 303 compatible = "abb,socrates-spi"; 304 reg = <3 0x60 0x10>; 305 interrupts = <8 4 0>; // number, type, routing 306 interrupt-parent = <&fpga_pic>; 307 }; 308 309 nand@3,70 { 310 compatible = "abb,socrates-nand"; 311 reg = <3 0x70 0x04>; 312 bank-width = <1>; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 data@0 { 316 label = "data"; 317 reg = <0x0 0x40000000>; 318 }; 319 }; 320 321 can@3,100 { 322 compatible = "philips,sja1000"; 323 reg = <3 0x100 0x80>; 324 interrupts = <2 8 1>; // number, type, routing 325 interrupt-parent = <&fpga_pic>; 326 }; 327 }; 328 329 pci0: pci@e0008000 { 330 #interrupt-cells = <1>; 331 #size-cells = <2>; 332 #address-cells = <3>; 333 compatible = "fsl,mpc8540-pci"; 334 device_type = "pci"; 335 reg = <0xe0008000 0x1000>; 336 clock-frequency = <66666666>; 337 338 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 339 interrupt-map = < 340 /* IDSEL 0x11 */ 341 0x8800 0x0 0x0 1 &mpic 5 1 342 /* IDSEL 0x12 */ 343 0x9000 0x0 0x0 1 &mpic 4 1>; 344 interrupt-parent = <&mpic>; 345 interrupts = <24 2>; 346 bus-range = <0x0 0x0>; 347 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 348 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>; 349 }; 350 351}; 352