1b6014e15SGiuseppe Coviello/* 2b6014e15SGiuseppe Coviello * Device Tree Source for ACube Sam440ep based off bamboo.dts code 3b6014e15SGiuseppe Coviello * original copyrights below 4b6014e15SGiuseppe Coviello * 5b6014e15SGiuseppe Coviello * Copyright (c) 2006, 2007 IBM Corp. 6b6014e15SGiuseppe Coviello * Josh Boyer <jwboyer@linux.vnet.ibm.com> 7b6014e15SGiuseppe Coviello * 8b6014e15SGiuseppe Coviello * Modified from bamboo.dts for sam440ep: 9b6014e15SGiuseppe Coviello * Copyright 2008 Giuseppe Coviello <gicoviello@gmail.com> 10b6014e15SGiuseppe Coviello * 11b6014e15SGiuseppe Coviello * This file is licensed under the terms of the GNU General Public 12b6014e15SGiuseppe Coviello * License version 2. This program is licensed "as is" without 13b6014e15SGiuseppe Coviello * any warranty of any kind, whether express or implied. 14b6014e15SGiuseppe Coviello */ 15b6014e15SGiuseppe Coviello 16b6014e15SGiuseppe Coviello/ { 17b6014e15SGiuseppe Coviello #address-cells = <2>; 18b6014e15SGiuseppe Coviello #size-cells = <1>; 19b6014e15SGiuseppe Coviello model = "acube,sam440ep"; 20b6014e15SGiuseppe Coviello compatible = "acube,sam440ep"; 21b6014e15SGiuseppe Coviello dcr-parent = <&/cpus/cpu@0>; 22b6014e15SGiuseppe Coviello 23b6014e15SGiuseppe Coviello aliases { 24b6014e15SGiuseppe Coviello ethernet0 = &EMAC0; 25b6014e15SGiuseppe Coviello ethernet1 = &EMAC1; 26b6014e15SGiuseppe Coviello serial0 = &UART0; 27b6014e15SGiuseppe Coviello serial1 = &UART1; 28b6014e15SGiuseppe Coviello serial2 = &UART2; 29b6014e15SGiuseppe Coviello serial3 = &UART3; 30b6014e15SGiuseppe Coviello }; 31b6014e15SGiuseppe Coviello 32b6014e15SGiuseppe Coviello cpus { 33b6014e15SGiuseppe Coviello #address-cells = <1>; 34b6014e15SGiuseppe Coviello #size-cells = <0>; 35b6014e15SGiuseppe Coviello 36b6014e15SGiuseppe Coviello cpu@0 { 37b6014e15SGiuseppe Coviello device_type = "cpu"; 38b6014e15SGiuseppe Coviello model = "PowerPC,440EP"; 39b6014e15SGiuseppe Coviello reg = <0>; 40b6014e15SGiuseppe Coviello clock-frequency = <0>; /* Filled in by zImage */ 41b6014e15SGiuseppe Coviello timebase-frequency = <0>; /* Filled in by zImage */ 42b6014e15SGiuseppe Coviello i-cache-line-size = <20>; 43b6014e15SGiuseppe Coviello d-cache-line-size = <20>; 44b6014e15SGiuseppe Coviello i-cache-size = <8000>; 45b6014e15SGiuseppe Coviello d-cache-size = <8000>; 46b6014e15SGiuseppe Coviello dcr-controller; 47b6014e15SGiuseppe Coviello dcr-access-method = "native"; 48b6014e15SGiuseppe Coviello }; 49b6014e15SGiuseppe Coviello }; 50b6014e15SGiuseppe Coviello 51b6014e15SGiuseppe Coviello memory { 52b6014e15SGiuseppe Coviello device_type = "memory"; 53b6014e15SGiuseppe Coviello reg = <0 0 0>; /* Filled in by zImage */ 54b6014e15SGiuseppe Coviello }; 55b6014e15SGiuseppe Coviello 56b6014e15SGiuseppe Coviello UIC0: interrupt-controller0 { 57b6014e15SGiuseppe Coviello compatible = "ibm,uic-440ep","ibm,uic"; 58b6014e15SGiuseppe Coviello interrupt-controller; 59b6014e15SGiuseppe Coviello cell-index = <0>; 60b6014e15SGiuseppe Coviello dcr-reg = <0c0 009>; 61b6014e15SGiuseppe Coviello #address-cells = <0>; 62b6014e15SGiuseppe Coviello #size-cells = <0>; 63b6014e15SGiuseppe Coviello #interrupt-cells = <2>; 64b6014e15SGiuseppe Coviello }; 65b6014e15SGiuseppe Coviello 66b6014e15SGiuseppe Coviello UIC1: interrupt-controller1 { 67b6014e15SGiuseppe Coviello compatible = "ibm,uic-440ep","ibm,uic"; 68b6014e15SGiuseppe Coviello interrupt-controller; 69b6014e15SGiuseppe Coviello cell-index = <1>; 70b6014e15SGiuseppe Coviello dcr-reg = <0d0 009>; 71b6014e15SGiuseppe Coviello #address-cells = <0>; 72b6014e15SGiuseppe Coviello #size-cells = <0>; 73b6014e15SGiuseppe Coviello #interrupt-cells = <2>; 74b6014e15SGiuseppe Coviello interrupts = <1e 4 1f 4>; /* cascade */ 75b6014e15SGiuseppe Coviello interrupt-parent = <&UIC0>; 76b6014e15SGiuseppe Coviello }; 77b6014e15SGiuseppe Coviello 78b6014e15SGiuseppe Coviello SDR0: sdr { 79b6014e15SGiuseppe Coviello compatible = "ibm,sdr-440ep"; 80b6014e15SGiuseppe Coviello dcr-reg = <00e 002>; 81b6014e15SGiuseppe Coviello }; 82b6014e15SGiuseppe Coviello 83b6014e15SGiuseppe Coviello CPR0: cpr { 84b6014e15SGiuseppe Coviello compatible = "ibm,cpr-440ep"; 85b6014e15SGiuseppe Coviello dcr-reg = <00c 002>; 86b6014e15SGiuseppe Coviello }; 87b6014e15SGiuseppe Coviello 88b6014e15SGiuseppe Coviello plb { 89b6014e15SGiuseppe Coviello compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4"; 90b6014e15SGiuseppe Coviello #address-cells = <2>; 91b6014e15SGiuseppe Coviello #size-cells = <1>; 92b6014e15SGiuseppe Coviello ranges; 93b6014e15SGiuseppe Coviello clock-frequency = <0>; /* Filled in by zImage */ 94b6014e15SGiuseppe Coviello 95b6014e15SGiuseppe Coviello SDRAM0: sdram { 96b6014e15SGiuseppe Coviello compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; 97b6014e15SGiuseppe Coviello dcr-reg = <010 2>; 98b6014e15SGiuseppe Coviello }; 99b6014e15SGiuseppe Coviello 100b6014e15SGiuseppe Coviello DMA0: dma { 101b6014e15SGiuseppe Coviello compatible = "ibm,dma-440ep", "ibm,dma-440gp"; 102b6014e15SGiuseppe Coviello dcr-reg = <100 027>; 103b6014e15SGiuseppe Coviello }; 104b6014e15SGiuseppe Coviello 105b6014e15SGiuseppe Coviello MAL0: mcmal { 106b6014e15SGiuseppe Coviello compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; 107b6014e15SGiuseppe Coviello dcr-reg = <180 62>; 108b6014e15SGiuseppe Coviello num-tx-chans = <4>; 109b6014e15SGiuseppe Coviello num-rx-chans = <2>; 110b6014e15SGiuseppe Coviello interrupt-parent = <&MAL0>; 111b6014e15SGiuseppe Coviello interrupts = <0 1 2 3 4>; 112b6014e15SGiuseppe Coviello #interrupt-cells = <1>; 113b6014e15SGiuseppe Coviello #address-cells = <0>; 114b6014e15SGiuseppe Coviello #size-cells = <0>; 115b6014e15SGiuseppe Coviello interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 116b6014e15SGiuseppe Coviello /*RXEOB*/ 1 &UIC0 b 4 117b6014e15SGiuseppe Coviello /*SERR*/ 2 &UIC1 0 4 118b6014e15SGiuseppe Coviello /*TXDE*/ 3 &UIC1 1 4 119b6014e15SGiuseppe Coviello /*RXDE*/ 4 &UIC1 2 4>; 120b6014e15SGiuseppe Coviello }; 121b6014e15SGiuseppe Coviello 122b6014e15SGiuseppe Coviello POB0: opb { 123b6014e15SGiuseppe Coviello compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb"; 124b6014e15SGiuseppe Coviello #address-cells = <1>; 125b6014e15SGiuseppe Coviello #size-cells = <1>; 126b6014e15SGiuseppe Coviello /* Bamboo is oddball in the 44x world and doesn't use the ERPN 127b6014e15SGiuseppe Coviello * bits. 128b6014e15SGiuseppe Coviello */ 129b6014e15SGiuseppe Coviello ranges = <00000000 0 00000000 80000000 130b6014e15SGiuseppe Coviello 80000000 0 80000000 80000000>; 131b6014e15SGiuseppe Coviello interrupt-parent = <&UIC1>; 132b6014e15SGiuseppe Coviello interrupts = <7 4>; 133b6014e15SGiuseppe Coviello clock-frequency = <0>; /* Filled in by zImage */ 134b6014e15SGiuseppe Coviello 135b6014e15SGiuseppe Coviello EBC0: ebc { 136b6014e15SGiuseppe Coviello compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; 137b6014e15SGiuseppe Coviello dcr-reg = <012 2>; 138b6014e15SGiuseppe Coviello #address-cells = <2>; 139b6014e15SGiuseppe Coviello #size-cells = <1>; 140b6014e15SGiuseppe Coviello clock-frequency = <0>; /* Filled in by zImage */ 141b6014e15SGiuseppe Coviello interrupts = <5 1>; 142b6014e15SGiuseppe Coviello interrupt-parent = <&UIC1>; 143b6014e15SGiuseppe Coviello }; 144b6014e15SGiuseppe Coviello 145b6014e15SGiuseppe Coviello UART0: serial@ef600300 { 146b6014e15SGiuseppe Coviello device_type = "serial"; 147b6014e15SGiuseppe Coviello compatible = "ns16550"; 148b6014e15SGiuseppe Coviello reg = <ef600300 8>; 149b6014e15SGiuseppe Coviello virtual-reg = <ef600300>; 150b6014e15SGiuseppe Coviello clock-frequency = <0>; /* Filled in by zImage */ 151b6014e15SGiuseppe Coviello current-speed = <1c200>; 152b6014e15SGiuseppe Coviello interrupt-parent = <&UIC0>; 153b6014e15SGiuseppe Coviello interrupts = <0 4>; 154b6014e15SGiuseppe Coviello }; 155b6014e15SGiuseppe Coviello 156b6014e15SGiuseppe Coviello UART1: serial@ef600400 { 157b6014e15SGiuseppe Coviello device_type = "serial"; 158b6014e15SGiuseppe Coviello compatible = "ns16550"; 159b6014e15SGiuseppe Coviello reg = <ef600400 8>; 160b6014e15SGiuseppe Coviello virtual-reg = <ef600400>; 161b6014e15SGiuseppe Coviello clock-frequency = <0>; 162b6014e15SGiuseppe Coviello current-speed = <0>; 163b6014e15SGiuseppe Coviello interrupt-parent = <&UIC0>; 164b6014e15SGiuseppe Coviello interrupts = <1 4>; 165b6014e15SGiuseppe Coviello }; 166b6014e15SGiuseppe Coviello 167b6014e15SGiuseppe Coviello UART2: serial@ef600500 { 168b6014e15SGiuseppe Coviello device_type = "serial"; 169b6014e15SGiuseppe Coviello compatible = "ns16550"; 170b6014e15SGiuseppe Coviello reg = <ef600500 8>; 171b6014e15SGiuseppe Coviello virtual-reg = <ef600500>; 172b6014e15SGiuseppe Coviello clock-frequency = <0>; 173b6014e15SGiuseppe Coviello current-speed = <0>; 174b6014e15SGiuseppe Coviello interrupt-parent = <&UIC0>; 175b6014e15SGiuseppe Coviello interrupts = <3 4>; 176b6014e15SGiuseppe Coviello }; 177b6014e15SGiuseppe Coviello 178b6014e15SGiuseppe Coviello UART3: serial@ef600600 { 179b6014e15SGiuseppe Coviello device_type = "serial"; 180b6014e15SGiuseppe Coviello compatible = "ns16550"; 181b6014e15SGiuseppe Coviello reg = <ef600600 8>; 182b6014e15SGiuseppe Coviello virtual-reg = <ef600600>; 183b6014e15SGiuseppe Coviello clock-frequency = <0>; 184b6014e15SGiuseppe Coviello current-speed = <0>; 185b6014e15SGiuseppe Coviello interrupt-parent = <&UIC0>; 186b6014e15SGiuseppe Coviello interrupts = <4 4>; 187b6014e15SGiuseppe Coviello }; 188b6014e15SGiuseppe Coviello 189b6014e15SGiuseppe Coviello IIC0: i2c@ef600700 { 190b6014e15SGiuseppe Coviello #address-cells = <1>; 191b6014e15SGiuseppe Coviello #size-cells = <0>; 192b6014e15SGiuseppe Coviello compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; 193b6014e15SGiuseppe Coviello index = <0>; 194b6014e15SGiuseppe Coviello reg = <ef600700 14>; 195b6014e15SGiuseppe Coviello interrupt-parent = <&UIC0>; 196b6014e15SGiuseppe Coviello interrupts = <2 4>; 197b6014e15SGiuseppe Coviello rtc@68 { 198b6014e15SGiuseppe Coviello compatible = "stm,m41t80"; 199b6014e15SGiuseppe Coviello reg = <68>; 200b6014e15SGiuseppe Coviello }; 201b6014e15SGiuseppe Coviello }; 202b6014e15SGiuseppe Coviello 203b6014e15SGiuseppe Coviello IIC1: i2c@ef600800 { 204b6014e15SGiuseppe Coviello compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; 205b6014e15SGiuseppe Coviello index = <5>; 206b6014e15SGiuseppe Coviello reg = <ef600800 14>; 207b6014e15SGiuseppe Coviello interrupt-parent = <&UIC0>; 208b6014e15SGiuseppe Coviello interrupts = <7 4>; 209b6014e15SGiuseppe Coviello }; 210b6014e15SGiuseppe Coviello 211b6014e15SGiuseppe Coviello ZMII0: emac-zmii@ef600d00 { 212b6014e15SGiuseppe Coviello compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; 213b6014e15SGiuseppe Coviello reg = <ef600d00 c>; 214b6014e15SGiuseppe Coviello }; 215b6014e15SGiuseppe Coviello 216b6014e15SGiuseppe Coviello EMAC0: ethernet@ef600e00 { 217b6014e15SGiuseppe Coviello linux,network-index = <0>; 218b6014e15SGiuseppe Coviello device_type = "network"; 219b6014e15SGiuseppe Coviello compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; 220b6014e15SGiuseppe Coviello interrupt-parent = <&UIC1>; 221b6014e15SGiuseppe Coviello interrupts = <1c 4 1d 4>; 222b6014e15SGiuseppe Coviello reg = <ef600e00 70>; 223b6014e15SGiuseppe Coviello local-mac-address = [000000000000]; 224b6014e15SGiuseppe Coviello mal-device = <&MAL0>; 225b6014e15SGiuseppe Coviello mal-tx-channel = <0 1>; 226b6014e15SGiuseppe Coviello mal-rx-channel = <0>; 227b6014e15SGiuseppe Coviello cell-index = <0>; 228b6014e15SGiuseppe Coviello max-frame-size = <5dc>; 229b6014e15SGiuseppe Coviello rx-fifo-size = <1000>; 230b6014e15SGiuseppe Coviello tx-fifo-size = <800>; 231b6014e15SGiuseppe Coviello phy-mode = "rmii"; 232b6014e15SGiuseppe Coviello phy-map = <00000000>; 233b6014e15SGiuseppe Coviello zmii-device = <&ZMII0>; 234b6014e15SGiuseppe Coviello zmii-channel = <0>; 235b6014e15SGiuseppe Coviello }; 236b6014e15SGiuseppe Coviello 237b6014e15SGiuseppe Coviello EMAC1: ethernet@ef600f00 { 238b6014e15SGiuseppe Coviello linux,network-index = <1>; 239b6014e15SGiuseppe Coviello device_type = "network"; 240b6014e15SGiuseppe Coviello compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; 241b6014e15SGiuseppe Coviello interrupt-parent = <&UIC1>; 242b6014e15SGiuseppe Coviello interrupts = <1e 4 1f 4>; 243b6014e15SGiuseppe Coviello reg = <ef600f00 70>; 244b6014e15SGiuseppe Coviello local-mac-address = [000000000000]; 245b6014e15SGiuseppe Coviello mal-device = <&MAL0>; 246b6014e15SGiuseppe Coviello mal-tx-channel = <2 3>; 247b6014e15SGiuseppe Coviello mal-rx-channel = <1>; 248b6014e15SGiuseppe Coviello cell-index = <1>; 249b6014e15SGiuseppe Coviello max-frame-size = <5dc>; 250b6014e15SGiuseppe Coviello rx-fifo-size = <1000>; 251b6014e15SGiuseppe Coviello tx-fifo-size = <800>; 252b6014e15SGiuseppe Coviello phy-mode = "rmii"; 253b6014e15SGiuseppe Coviello phy-map = <00000000>; 254b6014e15SGiuseppe Coviello zmii-device = <&ZMII0>; 255b6014e15SGiuseppe Coviello zmii-channel = <1>; 256b6014e15SGiuseppe Coviello }; 257b6014e15SGiuseppe Coviello usb@ef601000 { 258b6014e15SGiuseppe Coviello compatible = "ohci-be"; 259b6014e15SGiuseppe Coviello reg = <ef601000 80>; 260b6014e15SGiuseppe Coviello interrupts = <8 4 9 4>; 261b6014e15SGiuseppe Coviello interrupt-parent = < &UIC1 >; 262b6014e15SGiuseppe Coviello }; 263b6014e15SGiuseppe Coviello }; 264b6014e15SGiuseppe Coviello 265b6014e15SGiuseppe Coviello PCI0: pci@ec000000 { 266b6014e15SGiuseppe Coviello device_type = "pci"; 267b6014e15SGiuseppe Coviello #interrupt-cells = <1>; 268b6014e15SGiuseppe Coviello #size-cells = <2>; 269b6014e15SGiuseppe Coviello #address-cells = <3>; 270b6014e15SGiuseppe Coviello compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; 271b6014e15SGiuseppe Coviello primary; 272b6014e15SGiuseppe Coviello reg = <0 eec00000 8 /* Config space access */ 273b6014e15SGiuseppe Coviello 0 eed00000 4 /* IACK */ 274b6014e15SGiuseppe Coviello 0 eed00000 4 /* Special cycle */ 275b6014e15SGiuseppe Coviello 0 ef400000 40>; /* Internal registers */ 276b6014e15SGiuseppe Coviello 277b6014e15SGiuseppe Coviello /* Outbound ranges, one memory and one IO, 278b6014e15SGiuseppe Coviello * later cannot be changed. Chip supports a second 279b6014e15SGiuseppe Coviello * IO range but we don't use it for now 280b6014e15SGiuseppe Coviello */ 281b6014e15SGiuseppe Coviello ranges = <02000000 0 a0000000 0 a0000000 0 20000000 282b6014e15SGiuseppe Coviello 01000000 0 00000000 0 e8000000 0 00010000>; 283b6014e15SGiuseppe Coviello 284b6014e15SGiuseppe Coviello /* Inbound 2GB range starting at 0 */ 285b6014e15SGiuseppe Coviello dma-ranges = <42000000 0 0 0 0 0 80000000>; 286b6014e15SGiuseppe Coviello }; 287b6014e15SGiuseppe Coviello }; 288b6014e15SGiuseppe Coviello 289b6014e15SGiuseppe Coviello chosen { 290b6014e15SGiuseppe Coviello linux,stdout-path = "/plb/opb/serial@ef600300"; 291b6014e15SGiuseppe Coviello }; 292b6014e15SGiuseppe Coviello}; 293