1/* 2 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source 3 * 4 * Copyright (C) 2006-2009 Pengutronix 5 * Sascha Hauer <s.hauer@pengutronix.de> 6 * Juergen Beisert <j.beisert@pengutronix.de> 7 * Wolfram Sang <w.sang@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15/dts-v1/; 16 17/ { 18 model = "phytec,pcm032"; 19 compatible = "phytec,pcm032"; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 interrupt-parent = <&mpc5200_pic>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 PowerPC,5200@0 { 29 device_type = "cpu"; 30 reg = <0>; 31 d-cache-line-size = <32>; 32 i-cache-line-size = <32>; 33 d-cache-size = <0x4000>; // L1, 16K 34 i-cache-size = <0x4000>; // L1, 16K 35 timebase-frequency = <0>; // from bootloader 36 bus-frequency = <0>; // from bootloader 37 clock-frequency = <0>; // from bootloader 38 }; 39 }; 40 41 memory { 42 device_type = "memory"; 43 reg = <0x00000000 0x08000000>; // 128MB 44 }; 45 46 soc5200@f0000000 { 47 #address-cells = <1>; 48 #size-cells = <1>; 49 compatible = "fsl,mpc5200b-immr"; 50 ranges = <0 0xf0000000 0x0000c000>; 51 bus-frequency = <0>; // from bootloader 52 system-frequency = <0>; // from bootloader 53 54 cdm@200 { 55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 56 reg = <0x200 0x38>; 57 }; 58 59 mpc5200_pic: interrupt-controller@500 { 60 // 5200 interrupts are encoded into two levels; 61 interrupt-controller; 62 #interrupt-cells = <3>; 63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 64 reg = <0x500 0x80>; 65 }; 66 67 timer@600 { // General Purpose Timer 68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 69 reg = <0x600 0x10>; 70 interrupts = <1 9 0>; 71 fsl,has-wdt; 72 }; 73 74 timer@610 { // General Purpose Timer 75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 76 reg = <0x610 0x10>; 77 interrupts = <1 10 0>; 78 }; 79 80 gpt2: timer@620 { // General Purpose Timer in GPIO mode 81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 82 reg = <0x620 0x10>; 83 interrupts = <1 11 0>; 84 gpio-controller; 85 #gpio-cells = <2>; 86 }; 87 88 gpt3: timer@630 { // General Purpose Timer in GPIO mode 89 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 90 reg = <0x630 0x10>; 91 interrupts = <1 12 0>; 92 gpio-controller; 93 #gpio-cells = <2>; 94 }; 95 96 gpt4: timer@640 { // General Purpose Timer in GPIO mode 97 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 reg = <0x640 0x10>; 99 interrupts = <1 13 0>; 100 gpio-controller; 101 #gpio-cells = <2>; 102 }; 103 104 gpt5: timer@650 { // General Purpose Timer in GPIO mode 105 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 106 reg = <0x650 0x10>; 107 interrupts = <1 14 0>; 108 gpio-controller; 109 #gpio-cells = <2>; 110 }; 111 112 gpt6: timer@660 { // General Purpose Timer in GPIO mode 113 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 114 reg = <0x660 0x10>; 115 interrupts = <1 15 0>; 116 gpio-controller; 117 #gpio-cells = <2>; 118 }; 119 120 gpt7: timer@670 { // General Purpose Timer in GPIO mode 121 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 122 reg = <0x670 0x10>; 123 interrupts = <1 16 0>; 124 gpio-controller; 125 #gpio-cells = <2>; 126 }; 127 128 rtc@800 { // Real time clock 129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 130 reg = <0x800 0x100>; 131 interrupts = <1 5 0 1 6 0>; 132 }; 133 134 can@900 { 135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 136 interrupts = <2 17 0>; 137 reg = <0x900 0x80>; 138 }; 139 140 can@980 { 141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 142 interrupts = <2 18 0>; 143 reg = <0x980 0x80>; 144 }; 145 146 gpio_simple: gpio@b00 { 147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 148 reg = <0xb00 0x40>; 149 interrupts = <1 7 0>; 150 gpio-controller; 151 #gpio-cells = <2>; 152 }; 153 154 gpio_wkup: gpio@c00 { 155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 156 reg = <0xc00 0x40>; 157 interrupts = <1 8 0 0 3 0>; 158 gpio-controller; 159 #gpio-cells = <2>; 160 }; 161 162 spi@f00 { 163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 164 reg = <0xf00 0x20>; 165 interrupts = <2 13 0 2 14 0>; 166 }; 167 168 usb@1000 { 169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 170 reg = <0x1000 0xff>; 171 interrupts = <2 6 0>; 172 }; 173 174 dma-controller@1200 { 175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 176 reg = <0x1200 0x80>; 177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 178 3 4 0 3 5 0 3 6 0 3 7 0 179 3 8 0 3 9 0 3 10 0 3 11 0 180 3 12 0 3 13 0 3 14 0 3 15 0>; 181 }; 182 183 xlb@1f00 { 184 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 185 reg = <0x1f00 0x100>; 186 }; 187 188 ac97@2000 { /* PSC1 is ac97 */ 189 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 190 cell-index = <0>; 191 reg = <0x2000 0x100>; 192 interrupts = <2 1 0>; 193 }; 194 195 /* PSC2 port is used by CAN1/2 */ 196 197 serial@2400 { /* PSC3 in UART mode */ 198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 199 cell-index = <2>; 200 reg = <0x2400 0x100>; 201 interrupts = <2 3 0>; 202 }; 203 204 /* PSC4 is ??? */ 205 206 /* PSC5 is ??? */ 207 208 serial@2c00 { /* PSC6 in UART mode */ 209 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 210 cell-index = <5>; 211 reg = <0x2c00 0x100>; 212 interrupts = <2 4 0>; 213 }; 214 215 ethernet@3000 { 216 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 217 reg = <0x3000 0x400>; 218 local-mac-address = [ 00 00 00 00 00 00 ]; 219 interrupts = <2 5 0>; 220 phy-handle = <&phy0>; 221 }; 222 223 mdio@3000 { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 227 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 228 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 229 230 phy0: ethernet-phy@0 { 231 reg = <0>; 232 }; 233 }; 234 235 ata@3a00 { 236 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 237 reg = <0x3a00 0x100>; 238 interrupts = <2 7 0>; 239 }; 240 241 i2c@3d00 { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 245 reg = <0x3d00 0x40>; 246 interrupts = <2 15 0>; 247 fsl5200-clocking; 248 }; 249 250 i2c@3d40 { 251 #address-cells = <1>; 252 #size-cells = <0>; 253 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 254 reg = <0x3d40 0x40>; 255 interrupts = <2 16 0>; 256 fsl5200-clocking; 257 rtc@51 { 258 compatible = "nxp,pcf8563"; 259 reg = <0x51>; 260 }; 261 eeprom@52 { 262 compatible = "at24,24c32"; 263 reg = <0x52>; 264 }; 265 }; 266 267 sram@8000 { 268 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 269 reg = <0x8000 0x4000>; 270 }; 271 }; 272 273 pci@f0000d00 { 274 #interrupt-cells = <1>; 275 #size-cells = <2>; 276 #address-cells = <3>; 277 device_type = "pci"; 278 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 279 reg = <0xf0000d00 0x100>; 280 interrupt-map-mask = <0xf800 0 0 7>; 281 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 282 0xc000 0 0 2 &mpc5200_pic 1 1 3 283 0xc000 0 0 3 &mpc5200_pic 1 2 3 284 0xc000 0 0 4 &mpc5200_pic 1 3 3 285 286 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot 287 0xc800 0 0 2 &mpc5200_pic 1 2 3 288 0xc800 0 0 3 &mpc5200_pic 1 3 3 289 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 290 clock-frequency = <0>; // From boot loader 291 interrupts = <2 8 0 2 9 0 2 10 0>; 292 bus-range = <0 0>; 293 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 294 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 295 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 296 }; 297 298 localbus { 299 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus"; 300 301 #address-cells = <2>; 302 #size-cells = <1>; 303 304 ranges = <0 0 0xfe000000 0x02000000 305 1 0 0xfc000000 0x02000000 306 2 0 0xfbe00000 0x00200000 307 3 0 0xf9e00000 0x02000000 308 4 0 0xf7e00000 0x02000000 309 5 0 0xe6000000 0x02000000 310 6 0 0xe8000000 0x02000000 311 7 0 0xea000000 0x02000000>; 312 313 flash@0,0 { 314 compatible = "cfi-flash"; 315 reg = <0 0 0x02000000>; 316 bank-width = <4>; 317 #size-cells = <1>; 318 #address-cells = <1>; 319 320 partition@0 { 321 label = "ubootl"; 322 reg = <0x00000000 0x00040000>; 323 }; 324 partition@40000 { 325 label = "kernel"; 326 reg = <0x00040000 0x001c0000>; 327 }; 328 partition@200000 { 329 label = "jffs2"; 330 reg = <0x00200000 0x01d00000>; 331 }; 332 partition@1f00000 { 333 label = "uboot"; 334 reg = <0x01f00000 0x00040000>; 335 }; 336 partition@1f40000 { 337 label = "env"; 338 reg = <0x01f40000 0x00040000>; 339 }; 340 partition@1f80000 { 341 label = "oftree"; 342 reg = <0x01f80000 0x00040000>; 343 }; 344 partition@1fc0000 { 345 label = "space"; 346 reg = <0x01fc0000 0x00040000>; 347 }; 348 }; 349 350 sram@2,0 { 351 compatible = "mtd-ram"; 352 reg = <2 0 0x00200000>; 353 bank-width = <2>; 354 }; 355 356 /* 357 * example snippets for FPGA 358 * 359 * fpga@3,0 { 360 * compatible = "fpga_driver"; 361 * reg = <3 0 0x02000000>; 362 * bank-width = <4>; 363 * }; 364 * 365 * fpga@4,0 { 366 * compatible = "fpga_driver"; 367 * reg = <4 0 0x02000000>; 368 * bank-width = <4>; 369 * }; 370 */ 371 372 /* 373 * example snippets for free chipselects 374 * 375 * device@5,0 { 376 * compatible = "custom_driver"; 377 * reg = <5 0 0x02000000>; 378 * }; 379 * 380 * device@6,0 { 381 * compatible = "custom_driver"; 382 * reg = <6 0 0x02000000>; 383 * }; 384 * 385 * device@7,0 { 386 * compatible = "custom_driver"; 387 * reg = <7 0 0x02000000>; 388 * }; 389 */ 390 }; 391}; 392 393