1/*
2 * MPC8377E WLAN Device Tree Source
3 *
4 * Copyright 2007-2009 Freescale Semiconductor Inc.
5 * Copyright 2009 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16	compatible = "fsl,mpc8377wlan";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26		pci1 = &pci1;
27		pci2 = &pci2;
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		PowerPC,8377@0 {
35			device_type = "cpu";
36			reg = <0x0>;
37			d-cache-line-size = <32>;
38			i-cache-line-size = <32>;
39			d-cache-size = <32768>;
40			i-cache-size = <32768>;
41			timebase-frequency = <0>;
42			bus-frequency = <0>;
43			clock-frequency = <0>;
44		};
45	};
46
47	memory {
48		device_type = "memory";
49		reg = <0x00000000 0x20000000>;	// 512MB at 0
50	};
51
52	localbus@e0005000 {
53		#address-cells = <2>;
54		#size-cells = <1>;
55		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
56		reg = <0xe0005000 0x1000>;
57		interrupts = <77 0x8>;
58		interrupt-parent = <&ipic>;
59		ranges = <0x0 0x0 0xfc000000 0x04000000>;
60
61		flash@0,0 {
62			#address-cells = <1>;
63			#size-cells = <1>;
64			compatible = "cfi-flash";
65			reg = <0x0 0x0 0x4000000>;
66			bank-width = <2>;
67			device-width = <1>;
68
69			partition@0 {
70				reg = <0 0x80000>;
71				label = "u-boot";
72				read-only;
73			};
74
75			partition@a0000 {
76				reg = <0xa0000 0x300000>;
77				label = "kernel";
78			};
79
80			partition@3a0000 {
81				reg = <0x3a0000 0x3c60000>;
82				label = "rootfs";
83			};
84		};
85	};
86
87	immr@e0000000 {
88		#address-cells = <1>;
89		#size-cells = <1>;
90		device_type = "soc";
91		compatible = "simple-bus";
92		ranges = <0x0 0xe0000000 0x00100000>;
93		reg = <0xe0000000 0x00000200>;
94		bus-frequency = <0>;
95
96		wdt@200 {
97			device_type = "watchdog";
98			compatible = "mpc83xx_wdt";
99			reg = <0x200 0x100>;
100		};
101
102		gpio1: gpio-controller@c00 {
103			#gpio-cells = <2>;
104			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
105			reg = <0xc00 0x100>;
106			interrupts = <74 0x8>;
107			interrupt-parent = <&ipic>;
108			gpio-controller;
109		};
110
111		gpio2: gpio-controller@d00 {
112			#gpio-cells = <2>;
113			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
114			reg = <0xd00 0x100>;
115			interrupts = <75 0x8>;
116			interrupt-parent = <&ipic>;
117			gpio-controller;
118		};
119
120		sleep-nexus {
121			#address-cells = <1>;
122			#size-cells = <1>;
123			compatible = "simple-bus";
124			sleep = <&pmc 0x0c000000>;
125			ranges;
126
127			i2c@3000 {
128				#address-cells = <1>;
129				#size-cells = <0>;
130				cell-index = <0>;
131				compatible = "fsl-i2c";
132				reg = <0x3000 0x100>;
133				interrupts = <14 0x8>;
134				interrupt-parent = <&ipic>;
135				dfsrr;
136
137				at24@50 {
138					compatible = "at24,24c256";
139					reg = <0x50>;
140				};
141
142				rtc@68 {
143					compatible = "dallas,ds1339";
144					reg = <0x68>;
145				};
146			};
147
148			sdhci@2e000 {
149				compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
150				reg = <0x2e000 0x1000>;
151				interrupts = <42 0x8>;
152				interrupt-parent = <&ipic>;
153				sdhci,wp-inverted;
154				clock-frequency = <133333333>;
155			};
156		};
157
158		i2c@3100 {
159			#address-cells = <1>;
160			#size-cells = <0>;
161			cell-index = <1>;
162			compatible = "fsl-i2c";
163			reg = <0x3100 0x100>;
164			interrupts = <15 0x8>;
165			interrupt-parent = <&ipic>;
166			dfsrr;
167		};
168
169		spi@7000 {
170			cell-index = <0>;
171			compatible = "fsl,spi";
172			reg = <0x7000 0x1000>;
173			interrupts = <16 0x8>;
174			interrupt-parent = <&ipic>;
175			mode = "cpu";
176		};
177
178		dma@82a8 {
179			#address-cells = <1>;
180			#size-cells = <1>;
181			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
182			reg = <0x82a8 4>;
183			ranges = <0 0x8100 0x1a8>;
184			interrupt-parent = <&ipic>;
185			interrupts = <71 8>;
186			cell-index = <0>;
187			dma-channel@0 {
188				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
189				reg = <0 0x80>;
190				cell-index = <0>;
191				interrupt-parent = <&ipic>;
192				interrupts = <71 8>;
193			};
194			dma-channel@80 {
195				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
196				reg = <0x80 0x80>;
197				cell-index = <1>;
198				interrupt-parent = <&ipic>;
199				interrupts = <71 8>;
200			};
201			dma-channel@100 {
202				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
203				reg = <0x100 0x80>;
204				cell-index = <2>;
205				interrupt-parent = <&ipic>;
206				interrupts = <71 8>;
207			};
208			dma-channel@180 {
209				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
210				reg = <0x180 0x28>;
211				cell-index = <3>;
212				interrupt-parent = <&ipic>;
213				interrupts = <71 8>;
214			};
215		};
216
217		usb@23000 {
218			compatible = "fsl-usb2-dr";
219			reg = <0x23000 0x1000>;
220			#address-cells = <1>;
221			#size-cells = <0>;
222			interrupt-parent = <&ipic>;
223			interrupts = <38 0x8>;
224			phy_type = "ulpi";
225			sleep = <&pmc 0x00c00000>;
226		};
227
228		enet0: ethernet@24000 {
229			#address-cells = <1>;
230			#size-cells = <1>;
231			cell-index = <0>;
232			device_type = "network";
233			model = "eTSEC";
234			compatible = "gianfar";
235			reg = <0x24000 0x1000>;
236			ranges = <0x0 0x24000 0x1000>;
237			local-mac-address = [ 00 00 00 00 00 00 ];
238			interrupts = <32 0x8 33 0x8 34 0x8>;
239			phy-connection-type = "mii";
240			interrupt-parent = <&ipic>;
241			tbi-handle = <&tbi0>;
242			phy-handle = <&phy2>;
243			sleep = <&pmc 0xc0000000>;
244			fsl,magic-packet;
245
246			mdio@520 {
247				#address-cells = <1>;
248				#size-cells = <0>;
249				compatible = "fsl,gianfar-mdio";
250				reg = <0x520 0x20>;
251
252				phy2: ethernet-phy@2 {
253					interrupt-parent = <&ipic>;
254					interrupts = <17 0x8>;
255					reg = <0x2>;
256					device_type = "ethernet-phy";
257				};
258
259				phy3: ethernet-phy@3 {
260					interrupt-parent = <&ipic>;
261					interrupts = <18 0x8>;
262					reg = <0x3>;
263					device_type = "ethernet-phy";
264				};
265
266				tbi0: tbi-phy@11 {
267					reg = <0x11>;
268					device_type = "tbi-phy";
269				};
270			};
271		};
272
273		enet1: ethernet@25000 {
274			#address-cells = <1>;
275			#size-cells = <1>;
276			cell-index = <1>;
277			device_type = "network";
278			model = "eTSEC";
279			compatible = "gianfar";
280			reg = <0x25000 0x1000>;
281			ranges = <0x0 0x25000 0x1000>;
282			local-mac-address = [ 00 00 00 00 00 00 ];
283			interrupts = <35 0x8 36 0x8 37 0x8>;
284			phy-connection-type = "mii";
285			interrupt-parent = <&ipic>;
286			phy-handle = <&phy3>;
287			tbi-handle = <&tbi1>;
288			sleep = <&pmc 0x30000000>;
289			fsl,magic-packet;
290
291			mdio@520 {
292				#address-cells = <1>;
293				#size-cells = <0>;
294				compatible = "fsl,gianfar-tbi";
295				reg = <0x520 0x20>;
296
297				tbi1: tbi-phy@11 {
298					reg = <0x11>;
299					device_type = "tbi-phy";
300				};
301			};
302		};
303
304		serial0: serial@4500 {
305			cell-index = <0>;
306			device_type = "serial";
307			compatible = "fsl,ns16550", "ns16550";
308			reg = <0x4500 0x100>;
309			clock-frequency = <0>;
310			interrupts = <9 0x8>;
311			interrupt-parent = <&ipic>;
312		};
313
314		serial1: serial@4600 {
315			cell-index = <1>;
316			device_type = "serial";
317			compatible = "fsl,ns16550", "ns16550";
318			reg = <0x4600 0x100>;
319			clock-frequency = <0>;
320			interrupts = <10 0x8>;
321			interrupt-parent = <&ipic>;
322		};
323
324		crypto@30000 {
325			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
326				     "fsl,sec2.1", "fsl,sec2.0";
327			reg = <0x30000 0x10000>;
328			interrupts = <11 0x8>;
329			interrupt-parent = <&ipic>;
330			fsl,num-channels = <4>;
331			fsl,channel-fifo-len = <24>;
332			fsl,exec-units-mask = <0x9fe>;
333			fsl,descriptor-types-mask = <0x3ab0ebf>;
334			sleep = <&pmc 0x03000000>;
335		};
336
337		sata@18000 {
338			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
339			reg = <0x18000 0x1000>;
340			interrupts = <44 0x8>;
341			interrupt-parent = <&ipic>;
342			sleep = <&pmc 0x000000c0>;
343		};
344
345		sata@19000 {
346			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
347			reg = <0x19000 0x1000>;
348			interrupts = <45 0x8>;
349			interrupt-parent = <&ipic>;
350			sleep = <&pmc 0x00000030>;
351		};
352
353		/* IPIC
354		 * interrupts cell = <intr #, sense>
355		 * sense values match linux IORESOURCE_IRQ_* defines:
356		 * sense == 8: Level, low assertion
357		 * sense == 2: Edge, high-to-low change
358		 */
359		ipic: interrupt-controller@700 {
360			compatible = "fsl,ipic";
361			interrupt-controller;
362			#address-cells = <0>;
363			#interrupt-cells = <2>;
364			reg = <0x700 0x100>;
365		};
366
367		pmc: power@b00 {
368			compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
369			reg = <0xb00 0x100 0xa00 0x100>;
370			interrupts = <80 0x8>;
371			interrupt-parent = <&ipic>;
372		};
373	};
374
375	pci0: pci@e0008500 {
376		interrupt-map-mask = <0xf800 0 0 7>;
377		interrupt-map = <
378				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
379
380				/* IDSEL AD14 IRQ6 inta */
381				 0x7000 0x0 0x0 0x1 &ipic 22 0x8
382
383				/* IDSEL AD15 IRQ5 inta */
384				 0x7800 0x0 0x0 0x1 &ipic 21 0x8>;
385		interrupt-parent = <&ipic>;
386		interrupts = <66 0x8>;
387		bus-range = <0 0>;
388		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
389		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
390		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
391		sleep = <&pmc 0x00010000>;
392		clock-frequency = <66666666>;
393		#interrupt-cells = <1>;
394		#size-cells = <2>;
395		#address-cells = <3>;
396		reg = <0xe0008500 0x100		/* internal registers */
397		       0xe0008300 0x8>;		/* config space access registers */
398		compatible = "fsl,mpc8349-pci";
399		device_type = "pci";
400	};
401
402	pci1: pcie@e0009000 {
403		#address-cells = <3>;
404		#size-cells = <2>;
405		#interrupt-cells = <1>;
406		device_type = "pci";
407		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
408		reg = <0xe0009000 0x00001000>;
409		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
410		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
411		bus-range = <0 255>;
412		interrupt-map-mask = <0xf800 0 0 7>;
413		interrupt-map = <0 0 0 1 &ipic 1 8
414				 0 0 0 2 &ipic 1 8
415				 0 0 0 3 &ipic 1 8
416				 0 0 0 4 &ipic 1 8>;
417		sleep = <&pmc 0x00300000>;
418		clock-frequency = <0>;
419
420		pcie@0 {
421			#address-cells = <3>;
422			#size-cells = <2>;
423			device_type = "pci";
424			reg = <0 0 0 0 0>;
425			ranges = <0x02000000 0 0xa8000000
426				  0x02000000 0 0xa8000000
427				  0 0x10000000
428				  0x01000000 0 0x00000000
429				  0x01000000 0 0x00000000
430				  0 0x00800000>;
431		};
432	};
433
434	pci2: pcie@e000a000 {
435		#address-cells = <3>;
436		#size-cells = <2>;
437		#interrupt-cells = <1>;
438		device_type = "pci";
439		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
440		reg = <0xe000a000 0x00001000>;
441		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
442			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
443		bus-range = <0 255>;
444		interrupt-map-mask = <0xf800 0 0 7>;
445		interrupt-map = <0 0 0 1 &ipic 2 8
446				 0 0 0 2 &ipic 2 8
447				 0 0 0 3 &ipic 2 8
448				 0 0 0 4 &ipic 2 8>;
449		sleep = <&pmc 0x000c0000>;
450		clock-frequency = <0>;
451
452		pcie@0 {
453			#address-cells = <3>;
454			#size-cells = <2>;
455			device_type = "pci";
456			reg = <0 0 0 0 0>;
457			ranges = <0x02000000 0 0xc8000000
458				  0x02000000 0 0xc8000000
459				  0 0x10000000
460				  0x01000000 0 0x00000000
461				  0x01000000 0 0x00000000
462				  0 0x00800000>;
463		};
464	};
465};
466