1/*
2 * MPC8377E RDB Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	compatible = "fsl,mpc8377rdb";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		ethernet0 = &enet0;
21		ethernet1 = &enet1;
22		serial0 = &serial0;
23		serial1 = &serial1;
24		pci0 = &pci0;
25		pci1 = &pci1;
26		pci2 = &pci2;
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		PowerPC,8377@0 {
34			device_type = "cpu";
35			reg = <0x0>;
36			d-cache-line-size = <32>;
37			i-cache-line-size = <32>;
38			d-cache-size = <32768>;
39			i-cache-size = <32768>;
40			timebase-frequency = <0>;
41			bus-frequency = <0>;
42			clock-frequency = <0>;
43		};
44	};
45
46	memory {
47		device_type = "memory";
48		reg = <0x00000000 0x10000000>;	// 256MB at 0
49	};
50
51	localbus@e0005000 {
52		#address-cells = <2>;
53		#size-cells = <1>;
54		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
55		reg = <0xe0005000 0x1000>;
56		interrupts = <77 0x8>;
57		interrupt-parent = <&ipic>;
58
59		// CS0 and CS1 are swapped when
60		// booting from nand, but the
61		// addresses are the same.
62		ranges = <0x0 0x0 0xfe000000 0x00800000
63		          0x1 0x0 0xe0600000 0x00008000
64		          0x2 0x0 0xf0000000 0x00020000
65		          0x3 0x0 0xfa000000 0x00008000>;
66
67		flash@0,0 {
68			#address-cells = <1>;
69			#size-cells = <1>;
70			compatible = "cfi-flash";
71			reg = <0x0 0x0 0x800000>;
72			bank-width = <2>;
73			device-width = <1>;
74		};
75
76		nand@1,0 {
77			#address-cells = <1>;
78			#size-cells = <1>;
79			compatible = "fsl,mpc8377-fcm-nand",
80			             "fsl,elbc-fcm-nand";
81			reg = <0x1 0x0 0x8000>;
82
83			u-boot@0 {
84				reg = <0x0 0x100000>;
85				read-only;
86			};
87
88			kernel@100000 {
89				reg = <0x100000 0x300000>;
90			};
91			fs@400000 {
92				reg = <0x400000 0x1c00000>;
93			};
94		};
95	};
96
97	immr@e0000000 {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		device_type = "soc";
101		compatible = "simple-bus";
102		ranges = <0x0 0xe0000000 0x00100000>;
103		reg = <0xe0000000 0x00000200>;
104		bus-frequency = <0>;
105
106		wdt@200 {
107			device_type = "watchdog";
108			compatible = "mpc83xx_wdt";
109			reg = <0x200 0x100>;
110		};
111
112		gpio1: gpio-controller@c00 {
113			#gpio-cells = <2>;
114			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
115			reg = <0xc00 0x100>;
116			interrupts = <74 0x8>;
117			interrupt-parent = <&ipic>;
118			gpio-controller;
119		};
120
121		gpio2: gpio-controller@d00 {
122			#gpio-cells = <2>;
123			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
124			reg = <0xd00 0x100>;
125			interrupts = <75 0x8>;
126			interrupt-parent = <&ipic>;
127			gpio-controller;
128		};
129
130		i2c@3000 {
131			#address-cells = <1>;
132			#size-cells = <0>;
133			cell-index = <0>;
134			compatible = "fsl-i2c";
135			reg = <0x3000 0x100>;
136			interrupts = <14 0x8>;
137			interrupt-parent = <&ipic>;
138			dfsrr;
139
140			dtt@48 {
141				compatible = "national,lm75";
142				reg = <0x48>;
143			};
144
145			at24@50 {
146				compatible = "at24,24c256";
147				reg = <0x50>;
148			};
149
150			rtc@68 {
151				compatible = "dallas,ds1339";
152				reg = <0x68>;
153			};
154
155			mcu_pio: mcu@a {
156				#gpio-cells = <2>;
157				compatible = "fsl,mc9s08qg8-mpc8377erdb",
158					     "fsl,mcu-mpc8349emitx";
159				reg = <0x0a>;
160				gpio-controller;
161			};
162		};
163
164		i2c@3100 {
165			#address-cells = <1>;
166			#size-cells = <0>;
167			cell-index = <1>;
168			compatible = "fsl-i2c";
169			reg = <0x3100 0x100>;
170			interrupts = <15 0x8>;
171			interrupt-parent = <&ipic>;
172			dfsrr;
173		};
174
175		spi@7000 {
176			cell-index = <0>;
177			compatible = "fsl,spi";
178			reg = <0x7000 0x1000>;
179			interrupts = <16 0x8>;
180			interrupt-parent = <&ipic>;
181			mode = "cpu";
182		};
183
184		dma@82a8 {
185			#address-cells = <1>;
186			#size-cells = <1>;
187			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
188			reg = <0x82a8 4>;
189			ranges = <0 0x8100 0x1a8>;
190			interrupt-parent = <&ipic>;
191			interrupts = <71 8>;
192			cell-index = <0>;
193			dma-channel@0 {
194				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
195				reg = <0 0x80>;
196				cell-index = <0>;
197				interrupt-parent = <&ipic>;
198				interrupts = <71 8>;
199			};
200			dma-channel@80 {
201				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
202				reg = <0x80 0x80>;
203				cell-index = <1>;
204				interrupt-parent = <&ipic>;
205				interrupts = <71 8>;
206			};
207			dma-channel@100 {
208				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
209				reg = <0x100 0x80>;
210				cell-index = <2>;
211				interrupt-parent = <&ipic>;
212				interrupts = <71 8>;
213			};
214			dma-channel@180 {
215				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
216				reg = <0x180 0x28>;
217				cell-index = <3>;
218				interrupt-parent = <&ipic>;
219				interrupts = <71 8>;
220			};
221		};
222
223		usb@23000 {
224			compatible = "fsl-usb2-dr";
225			reg = <0x23000 0x1000>;
226			#address-cells = <1>;
227			#size-cells = <0>;
228			interrupt-parent = <&ipic>;
229			interrupts = <38 0x8>;
230			phy_type = "ulpi";
231		};
232
233		mdio@24520 {
234			#address-cells = <1>;
235			#size-cells = <0>;
236			compatible = "fsl,gianfar-mdio";
237			reg = <0x24520 0x20>;
238			phy2: ethernet-phy@2 {
239				interrupt-parent = <&ipic>;
240				interrupts = <17 0x8>;
241				reg = <0x2>;
242				device_type = "ethernet-phy";
243			};
244			tbi0: tbi-phy@11 {
245				reg = <0x11>;
246				device_type = "tbi-phy";
247			};
248		};
249
250		mdio@25520 {
251			#address-cells = <1>;
252			#size-cells = <0>;
253			compatible = "fsl,gianfar-tbi";
254			reg = <0x25520 0x20>;
255
256			tbi1: tbi-phy@11 {
257				reg = <0x11>;
258				device_type = "tbi-phy";
259			};
260		};
261
262
263		enet0: ethernet@24000 {
264			cell-index = <0>;
265			device_type = "network";
266			model = "eTSEC";
267			compatible = "gianfar";
268			reg = <0x24000 0x1000>;
269			local-mac-address = [ 00 00 00 00 00 00 ];
270			interrupts = <32 0x8 33 0x8 34 0x8>;
271			phy-connection-type = "mii";
272			interrupt-parent = <&ipic>;
273			tbi-handle = <&tbi0>;
274			phy-handle = <&phy2>;
275		};
276
277		enet1: ethernet@25000 {
278			cell-index = <1>;
279			device_type = "network";
280			model = "eTSEC";
281			compatible = "gianfar";
282			reg = <0x25000 0x1000>;
283			local-mac-address = [ 00 00 00 00 00 00 ];
284			interrupts = <35 0x8 36 0x8 37 0x8>;
285			phy-connection-type = "mii";
286			interrupt-parent = <&ipic>;
287			fixed-link = <1 1 1000 0 0>;
288			tbi-handle = <&tbi1>;
289		};
290
291		serial0: serial@4500 {
292			cell-index = <0>;
293			device_type = "serial";
294			compatible = "ns16550";
295			reg = <0x4500 0x100>;
296			clock-frequency = <0>;
297			interrupts = <9 0x8>;
298			interrupt-parent = <&ipic>;
299		};
300
301		serial1: serial@4600 {
302			cell-index = <1>;
303			device_type = "serial";
304			compatible = "ns16550";
305			reg = <0x4600 0x100>;
306			clock-frequency = <0>;
307			interrupts = <10 0x8>;
308			interrupt-parent = <&ipic>;
309		};
310
311		crypto@30000 {
312			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
313				     "fsl,sec2.1", "fsl,sec2.0";
314			reg = <0x30000 0x10000>;
315			interrupts = <11 0x8>;
316			interrupt-parent = <&ipic>;
317			fsl,num-channels = <4>;
318			fsl,channel-fifo-len = <24>;
319			fsl,exec-units-mask = <0x9fe>;
320			fsl,descriptor-types-mask = <0x3ab0ebf>;
321		};
322
323		sdhci@2e000 {
324			compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
325			reg = <0x2e000 0x1000>;
326			interrupts = <42 0x8>;
327			interrupt-parent = <&ipic>;
328			/* Filled in by U-Boot */
329			clock-frequency = <0>;
330		};
331
332		sata@18000 {
333			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
334			reg = <0x18000 0x1000>;
335			interrupts = <44 0x8>;
336			interrupt-parent = <&ipic>;
337		};
338
339		sata@19000 {
340			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
341			reg = <0x19000 0x1000>;
342			interrupts = <45 0x8>;
343			interrupt-parent = <&ipic>;
344		};
345
346		/* IPIC
347		 * interrupts cell = <intr #, sense>
348		 * sense values match linux IORESOURCE_IRQ_* defines:
349		 * sense == 8: Level, low assertion
350		 * sense == 2: Edge, high-to-low change
351		 */
352		ipic: interrupt-controller@700 {
353			compatible = "fsl,ipic";
354			interrupt-controller;
355			#address-cells = <0>;
356			#interrupt-cells = <2>;
357			reg = <0x700 0x100>;
358		};
359	};
360
361	pci0: pci@e0008500 {
362		interrupt-map-mask = <0xf800 0 0 7>;
363		interrupt-map = <
364				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
365
366				/* IDSEL AD14 IRQ6 inta */
367				 0x7000 0x0 0x0 0x1 &ipic 22 0x8
368
369				/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
370				 0x7800 0x0 0x0 0x1 &ipic 21 0x8
371				 0x7800 0x0 0x0 0x2 &ipic 22 0x8
372				 0x7800 0x0 0x0 0x4 &ipic 23 0x8
373
374				/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
375				 0xE000 0x0 0x0 0x1 &ipic 23 0x8
376				 0xE000 0x0 0x0 0x2 &ipic 21 0x8
377				 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
378		interrupt-parent = <&ipic>;
379		interrupts = <66 0x8>;
380		bus-range = <0 0>;
381		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
382		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
383		          0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
384		clock-frequency = <66666666>;
385		#interrupt-cells = <1>;
386		#size-cells = <2>;
387		#address-cells = <3>;
388		reg = <0xe0008500 0x100		/* internal registers */
389		       0xe0008300 0x8>;		/* config space access registers */
390		compatible = "fsl,mpc8349-pci";
391		device_type = "pci";
392	};
393
394	pci1: pcie@e0009000 {
395		#address-cells = <3>;
396		#size-cells = <2>;
397		#interrupt-cells = <1>;
398		device_type = "pci";
399		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
400		reg = <0xe0009000 0x00001000>;
401		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
402		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
403		bus-range = <0 255>;
404		interrupt-map-mask = <0xf800 0 0 7>;
405		interrupt-map = <0 0 0 1 &ipic 1 8
406				 0 0 0 2 &ipic 1 8
407				 0 0 0 3 &ipic 1 8
408				 0 0 0 4 &ipic 1 8>;
409		clock-frequency = <0>;
410
411		pcie@0 {
412			#address-cells = <3>;
413			#size-cells = <2>;
414			device_type = "pci";
415			reg = <0 0 0 0 0>;
416			ranges = <0x02000000 0 0xa8000000
417				  0x02000000 0 0xa8000000
418				  0 0x10000000
419				  0x01000000 0 0x00000000
420				  0x01000000 0 0x00000000
421				  0 0x00800000>;
422		};
423	};
424
425	pci2: pcie@e000a000 {
426		#address-cells = <3>;
427		#size-cells = <2>;
428		#interrupt-cells = <1>;
429		device_type = "pci";
430		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
431		reg = <0xe000a000 0x00001000>;
432		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
433			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
434		bus-range = <0 255>;
435		interrupt-map-mask = <0xf800 0 0 7>;
436		interrupt-map = <0 0 0 1 &ipic 2 8
437				 0 0 0 2 &ipic 2 8
438				 0 0 0 3 &ipic 2 8
439				 0 0 0 4 &ipic 2 8>;
440		clock-frequency = <0>;
441
442		pcie@0 {
443			#address-cells = <3>;
444			#size-cells = <2>;
445			device_type = "pci";
446			reg = <0 0 0 0 0>;
447			ranges = <0x02000000 0 0xc8000000
448				  0x02000000 0 0xc8000000
449				  0 0x10000000
450				  0x01000000 0 0x00000000
451				  0x01000000 0 0x00000000
452				  0 0x00800000>;
453		};
454	};
455};
456