1/* 2 * MPC8377E RDB Device Tree Source 3 * 4 * Copyright 2007, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 compatible = "fsl,mpc8377rdb"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 ethernet0 = &enet0; 21 ethernet1 = &enet1; 22 serial0 = &serial0; 23 serial1 = &serial1; 24 pci0 = &pci0; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 PowerPC,8377@0 { 32 device_type = "cpu"; 33 reg = <0x0>; 34 d-cache-line-size = <32>; 35 i-cache-line-size = <32>; 36 d-cache-size = <32768>; 37 i-cache-size = <32768>; 38 timebase-frequency = <0>; 39 bus-frequency = <0>; 40 clock-frequency = <0>; 41 }; 42 }; 43 44 memory { 45 device_type = "memory"; 46 reg = <0x00000000 0x10000000>; // 256MB at 0 47 }; 48 49 localbus@e0005000 { 50 #address-cells = <2>; 51 #size-cells = <1>; 52 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus"; 53 reg = <0xe0005000 0x1000>; 54 interrupts = <77 0x8>; 55 interrupt-parent = <&ipic>; 56 57 // CS0 and CS1 are swapped when 58 // booting from nand, but the 59 // addresses are the same. 60 ranges = <0x0 0x0 0xfe000000 0x00800000 61 0x1 0x0 0xe0600000 0x00008000 62 0x2 0x0 0xf0000000 0x00020000 63 0x3 0x0 0xfa000000 0x00008000>; 64 65 flash@0,0 { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 compatible = "cfi-flash"; 69 reg = <0x0 0x0 0x800000>; 70 bank-width = <2>; 71 device-width = <1>; 72 }; 73 74 nand@1,0 { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 compatible = "fsl,mpc8377-fcm-nand", 78 "fsl,elbc-fcm-nand"; 79 reg = <0x1 0x0 0x8000>; 80 81 u-boot@0 { 82 reg = <0x0 0x100000>; 83 read-only; 84 }; 85 86 kernel@100000 { 87 reg = <0x100000 0x300000>; 88 }; 89 fs@400000 { 90 reg = <0x400000 0x1c00000>; 91 }; 92 }; 93 }; 94 95 immr@e0000000 { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 device_type = "soc"; 99 compatible = "simple-bus"; 100 ranges = <0x0 0xe0000000 0x00100000>; 101 reg = <0xe0000000 0x00000200>; 102 bus-frequency = <0>; 103 104 wdt@200 { 105 device_type = "watchdog"; 106 compatible = "mpc83xx_wdt"; 107 reg = <0x200 0x100>; 108 }; 109 110 i2c@3000 { 111 #address-cells = <1>; 112 #size-cells = <0>; 113 cell-index = <0>; 114 compatible = "fsl-i2c"; 115 reg = <0x3000 0x100>; 116 interrupts = <14 0x8>; 117 interrupt-parent = <&ipic>; 118 dfsrr; 119 rtc@68 { 120 compatible = "dallas,ds1339"; 121 reg = <0x68>; 122 }; 123 124 mcu_pio: mcu@a { 125 #gpio-cells = <2>; 126 compatible = "fsl,mc9s08qg8-mpc8377erdb", 127 "fsl,mcu-mpc8349emitx"; 128 reg = <0x0a>; 129 gpio-controller; 130 }; 131 }; 132 133 i2c@3100 { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 cell-index = <1>; 137 compatible = "fsl-i2c"; 138 reg = <0x3100 0x100>; 139 interrupts = <15 0x8>; 140 interrupt-parent = <&ipic>; 141 dfsrr; 142 }; 143 144 spi@7000 { 145 cell-index = <0>; 146 compatible = "fsl,spi"; 147 reg = <0x7000 0x1000>; 148 interrupts = <16 0x8>; 149 interrupt-parent = <&ipic>; 150 mode = "cpu"; 151 }; 152 153 dma@82a8 { 154 #address-cells = <1>; 155 #size-cells = <1>; 156 compatible = "fsl,mpc8377-dma", "fsl,elo-dma"; 157 reg = <0x82a8 4>; 158 ranges = <0 0x8100 0x1a8>; 159 interrupt-parent = <&ipic>; 160 interrupts = <71 8>; 161 cell-index = <0>; 162 dma-channel@0 { 163 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; 164 reg = <0 0x80>; 165 cell-index = <0>; 166 interrupt-parent = <&ipic>; 167 interrupts = <71 8>; 168 }; 169 dma-channel@80 { 170 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; 171 reg = <0x80 0x80>; 172 cell-index = <1>; 173 interrupt-parent = <&ipic>; 174 interrupts = <71 8>; 175 }; 176 dma-channel@100 { 177 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; 178 reg = <0x100 0x80>; 179 cell-index = <2>; 180 interrupt-parent = <&ipic>; 181 interrupts = <71 8>; 182 }; 183 dma-channel@180 { 184 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; 185 reg = <0x180 0x28>; 186 cell-index = <3>; 187 interrupt-parent = <&ipic>; 188 interrupts = <71 8>; 189 }; 190 }; 191 192 usb@23000 { 193 compatible = "fsl-usb2-dr"; 194 reg = <0x23000 0x1000>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 interrupt-parent = <&ipic>; 198 interrupts = <38 0x8>; 199 phy_type = "ulpi"; 200 }; 201 202 mdio@24520 { 203 #address-cells = <1>; 204 #size-cells = <0>; 205 compatible = "fsl,gianfar-mdio"; 206 reg = <0x24520 0x20>; 207 phy2: ethernet-phy@2 { 208 interrupt-parent = <&ipic>; 209 interrupts = <17 0x8>; 210 reg = <0x2>; 211 device_type = "ethernet-phy"; 212 }; 213 }; 214 215 enet0: ethernet@24000 { 216 cell-index = <0>; 217 device_type = "network"; 218 model = "eTSEC"; 219 compatible = "gianfar"; 220 reg = <0x24000 0x1000>; 221 local-mac-address = [ 00 00 00 00 00 00 ]; 222 interrupts = <32 0x8 33 0x8 34 0x8>; 223 phy-connection-type = "mii"; 224 interrupt-parent = <&ipic>; 225 phy-handle = <&phy2>; 226 }; 227 228 enet1: ethernet@25000 { 229 cell-index = <1>; 230 device_type = "network"; 231 model = "eTSEC"; 232 compatible = "gianfar"; 233 reg = <0x25000 0x1000>; 234 local-mac-address = [ 00 00 00 00 00 00 ]; 235 interrupts = <35 0x8 36 0x8 37 0x8>; 236 phy-connection-type = "mii"; 237 interrupt-parent = <&ipic>; 238 fixed-link = <1 1 1000 0 0>; 239 }; 240 241 serial0: serial@4500 { 242 cell-index = <0>; 243 device_type = "serial"; 244 compatible = "ns16550"; 245 reg = <0x4500 0x100>; 246 clock-frequency = <0>; 247 interrupts = <9 0x8>; 248 interrupt-parent = <&ipic>; 249 }; 250 251 serial1: serial@4600 { 252 cell-index = <1>; 253 device_type = "serial"; 254 compatible = "ns16550"; 255 reg = <0x4600 0x100>; 256 clock-frequency = <0>; 257 interrupts = <10 0x8>; 258 interrupt-parent = <&ipic>; 259 }; 260 261 crypto@30000 { 262 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 263 "fsl,sec2.1", "fsl,sec2.0"; 264 reg = <0x30000 0x10000>; 265 interrupts = <11 0x8>; 266 interrupt-parent = <&ipic>; 267 fsl,num-channels = <4>; 268 fsl,channel-fifo-len = <24>; 269 fsl,exec-units-mask = <0x9fe>; 270 fsl,descriptor-types-mask = <0x3ab0ebf>; 271 }; 272 273 sata@18000 { 274 compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; 275 reg = <0x18000 0x1000>; 276 interrupts = <44 0x8>; 277 interrupt-parent = <&ipic>; 278 }; 279 280 sata@19000 { 281 compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; 282 reg = <0x19000 0x1000>; 283 interrupts = <45 0x8>; 284 interrupt-parent = <&ipic>; 285 }; 286 287 /* IPIC 288 * interrupts cell = <intr #, sense> 289 * sense values match linux IORESOURCE_IRQ_* defines: 290 * sense == 8: Level, low assertion 291 * sense == 2: Edge, high-to-low change 292 */ 293 ipic: interrupt-controller@700 { 294 compatible = "fsl,ipic"; 295 interrupt-controller; 296 #address-cells = <0>; 297 #interrupt-cells = <2>; 298 reg = <0x700 0x100>; 299 }; 300 }; 301 302 pci0: pci@e0008500 { 303 interrupt-map-mask = <0xf800 0 0 7>; 304 interrupt-map = < 305 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ 306 307 /* IDSEL AD14 IRQ6 inta */ 308 0x7000 0x0 0x0 0x1 &ipic 22 0x8 309 310 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ 311 0x7800 0x0 0x0 0x1 &ipic 21 0x8 312 0x7800 0x0 0x0 0x2 &ipic 22 0x8 313 0x7800 0x0 0x0 0x4 &ipic 23 0x8 314 315 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ 316 0xE000 0x0 0x0 0x1 &ipic 23 0x8 317 0xE000 0x0 0x0 0x2 &ipic 21 0x8 318 0xE000 0x0 0x0 0x3 &ipic 22 0x8>; 319 interrupt-parent = <&ipic>; 320 interrupts = <66 0x8>; 321 bus-range = <0 0>; 322 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 323 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 324 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 325 clock-frequency = <66666666>; 326 #interrupt-cells = <1>; 327 #size-cells = <2>; 328 #address-cells = <3>; 329 reg = <0xe0008500 0x100 /* internal registers */ 330 0xe0008300 0x8>; /* config space access registers */ 331 compatible = "fsl,mpc8349-pci"; 332 device_type = "pci"; 333 }; 334}; 335