1/*
2 * MPC8377E RDB Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	compatible = "fsl,mpc8377rdb";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		ethernet0 = &enet0;
21		ethernet1 = &enet1;
22		serial0 = &serial0;
23		serial1 = &serial1;
24		pci0 = &pci0;
25		pci1 = &pci1;
26		pci2 = &pci2;
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		PowerPC,8377@0 {
34			device_type = "cpu";
35			reg = <0x0>;
36			d-cache-line-size = <32>;
37			i-cache-line-size = <32>;
38			d-cache-size = <32768>;
39			i-cache-size = <32768>;
40			timebase-frequency = <0>;
41			bus-frequency = <0>;
42			clock-frequency = <0>;
43		};
44	};
45
46	memory {
47		device_type = "memory";
48		reg = <0x00000000 0x10000000>;	// 256MB at 0
49	};
50
51	localbus@e0005000 {
52		#address-cells = <2>;
53		#size-cells = <1>;
54		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
55		reg = <0xe0005000 0x1000>;
56		interrupts = <77 0x8>;
57		interrupt-parent = <&ipic>;
58
59		// CS0 and CS1 are swapped when
60		// booting from nand, but the
61		// addresses are the same.
62		ranges = <0x0 0x0 0xfe000000 0x00800000
63		          0x1 0x0 0xe0600000 0x00008000
64		          0x2 0x0 0xf0000000 0x00020000
65		          0x3 0x0 0xfa000000 0x00008000>;
66
67		flash@0,0 {
68			#address-cells = <1>;
69			#size-cells = <1>;
70			compatible = "cfi-flash";
71			reg = <0x0 0x0 0x800000>;
72			bank-width = <2>;
73			device-width = <1>;
74		};
75
76		nand@1,0 {
77			#address-cells = <1>;
78			#size-cells = <1>;
79			compatible = "fsl,mpc8377-fcm-nand",
80			             "fsl,elbc-fcm-nand";
81			reg = <0x1 0x0 0x8000>;
82
83			u-boot@0 {
84				reg = <0x0 0x100000>;
85				read-only;
86			};
87
88			kernel@100000 {
89				reg = <0x100000 0x300000>;
90			};
91			fs@400000 {
92				reg = <0x400000 0x1c00000>;
93			};
94		};
95	};
96
97	immr@e0000000 {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		device_type = "soc";
101		compatible = "simple-bus";
102		ranges = <0x0 0xe0000000 0x00100000>;
103		reg = <0xe0000000 0x00000200>;
104		bus-frequency = <0>;
105
106		wdt@200 {
107			device_type = "watchdog";
108			compatible = "mpc83xx_wdt";
109			reg = <0x200 0x100>;
110		};
111
112		gpio1: gpio-controller@c00 {
113			#gpio-cells = <2>;
114			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
115			reg = <0xc00 0x100>;
116			interrupts = <74 0x8>;
117			interrupt-parent = <&ipic>;
118			gpio-controller;
119		};
120
121		gpio2: gpio-controller@d00 {
122			#gpio-cells = <2>;
123			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
124			reg = <0xd00 0x100>;
125			interrupts = <75 0x8>;
126			interrupt-parent = <&ipic>;
127			gpio-controller;
128		};
129
130		sleep-nexus {
131			#address-cells = <1>;
132			#size-cells = <1>;
133			compatible = "simple-bus";
134			sleep = <&pmc 0x0c000000>;
135			ranges;
136
137			i2c@3000 {
138				#address-cells = <1>;
139				#size-cells = <0>;
140				cell-index = <0>;
141				compatible = "fsl-i2c";
142				reg = <0x3000 0x100>;
143				interrupts = <14 0x8>;
144				interrupt-parent = <&ipic>;
145				dfsrr;
146
147				dtt@48 {
148					compatible = "national,lm75";
149					reg = <0x48>;
150				};
151
152				at24@50 {
153					compatible = "at24,24c256";
154					reg = <0x50>;
155				};
156
157				rtc@68 {
158					compatible = "dallas,ds1339";
159					reg = <0x68>;
160				};
161
162				mcu_pio: mcu@a {
163					#gpio-cells = <2>;
164					compatible = "fsl,mc9s08qg8-mpc8377erdb",
165						     "fsl,mcu-mpc8349emitx";
166					reg = <0x0a>;
167					gpio-controller;
168				};
169			};
170
171			sdhci@2e000 {
172				compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
173				reg = <0x2e000 0x1000>;
174				interrupts = <42 0x8>;
175				interrupt-parent = <&ipic>;
176				/* Filled in by U-Boot */
177				clock-frequency = <0>;
178			};
179		};
180
181		i2c@3100 {
182			#address-cells = <1>;
183			#size-cells = <0>;
184			cell-index = <1>;
185			compatible = "fsl-i2c";
186			reg = <0x3100 0x100>;
187			interrupts = <15 0x8>;
188			interrupt-parent = <&ipic>;
189			dfsrr;
190		};
191
192		spi@7000 {
193			cell-index = <0>;
194			compatible = "fsl,spi";
195			reg = <0x7000 0x1000>;
196			interrupts = <16 0x8>;
197			interrupt-parent = <&ipic>;
198			mode = "cpu";
199		};
200
201		dma@82a8 {
202			#address-cells = <1>;
203			#size-cells = <1>;
204			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
205			reg = <0x82a8 4>;
206			ranges = <0 0x8100 0x1a8>;
207			interrupt-parent = <&ipic>;
208			interrupts = <71 8>;
209			cell-index = <0>;
210			dma-channel@0 {
211				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
212				reg = <0 0x80>;
213				cell-index = <0>;
214				interrupt-parent = <&ipic>;
215				interrupts = <71 8>;
216			};
217			dma-channel@80 {
218				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
219				reg = <0x80 0x80>;
220				cell-index = <1>;
221				interrupt-parent = <&ipic>;
222				interrupts = <71 8>;
223			};
224			dma-channel@100 {
225				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
226				reg = <0x100 0x80>;
227				cell-index = <2>;
228				interrupt-parent = <&ipic>;
229				interrupts = <71 8>;
230			};
231			dma-channel@180 {
232				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
233				reg = <0x180 0x28>;
234				cell-index = <3>;
235				interrupt-parent = <&ipic>;
236				interrupts = <71 8>;
237			};
238		};
239
240		usb@23000 {
241			compatible = "fsl-usb2-dr";
242			reg = <0x23000 0x1000>;
243			#address-cells = <1>;
244			#size-cells = <0>;
245			interrupt-parent = <&ipic>;
246			interrupts = <38 0x8>;
247			phy_type = "ulpi";
248			sleep = <&pmc 0x00c00000>;
249		};
250
251		mdio@24520 {
252			#address-cells = <1>;
253			#size-cells = <0>;
254			compatible = "fsl,gianfar-mdio";
255			reg = <0x24520 0x20>;
256			phy2: ethernet-phy@2 {
257				interrupt-parent = <&ipic>;
258				interrupts = <17 0x8>;
259				reg = <0x2>;
260				device_type = "ethernet-phy";
261			};
262			tbi0: tbi-phy@11 {
263				reg = <0x11>;
264				device_type = "tbi-phy";
265			};
266		};
267
268		mdio@25520 {
269			#address-cells = <1>;
270			#size-cells = <0>;
271			compatible = "fsl,gianfar-tbi";
272			reg = <0x25520 0x20>;
273
274			tbi1: tbi-phy@11 {
275				reg = <0x11>;
276				device_type = "tbi-phy";
277			};
278		};
279
280
281		enet0: ethernet@24000 {
282			cell-index = <0>;
283			device_type = "network";
284			model = "eTSEC";
285			compatible = "gianfar";
286			reg = <0x24000 0x1000>;
287			local-mac-address = [ 00 00 00 00 00 00 ];
288			interrupts = <32 0x8 33 0x8 34 0x8>;
289			phy-connection-type = "mii";
290			interrupt-parent = <&ipic>;
291			tbi-handle = <&tbi0>;
292			phy-handle = <&phy2>;
293			sleep = <&pmc 0xc0000000>;
294			fsl,magic-packet;
295		};
296
297		enet1: ethernet@25000 {
298			cell-index = <1>;
299			device_type = "network";
300			model = "eTSEC";
301			compatible = "gianfar";
302			reg = <0x25000 0x1000>;
303			local-mac-address = [ 00 00 00 00 00 00 ];
304			interrupts = <35 0x8 36 0x8 37 0x8>;
305			phy-connection-type = "mii";
306			interrupt-parent = <&ipic>;
307			fixed-link = <1 1 1000 0 0>;
308			tbi-handle = <&tbi1>;
309			sleep = <&pmc 0x30000000>;
310			fsl,magic-packet;
311		};
312
313		serial0: serial@4500 {
314			cell-index = <0>;
315			device_type = "serial";
316			compatible = "ns16550";
317			reg = <0x4500 0x100>;
318			clock-frequency = <0>;
319			interrupts = <9 0x8>;
320			interrupt-parent = <&ipic>;
321		};
322
323		serial1: serial@4600 {
324			cell-index = <1>;
325			device_type = "serial";
326			compatible = "ns16550";
327			reg = <0x4600 0x100>;
328			clock-frequency = <0>;
329			interrupts = <10 0x8>;
330			interrupt-parent = <&ipic>;
331		};
332
333		crypto@30000 {
334			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
335				     "fsl,sec2.1", "fsl,sec2.0";
336			reg = <0x30000 0x10000>;
337			interrupts = <11 0x8>;
338			interrupt-parent = <&ipic>;
339			fsl,num-channels = <4>;
340			fsl,channel-fifo-len = <24>;
341			fsl,exec-units-mask = <0x9fe>;
342			fsl,descriptor-types-mask = <0x3ab0ebf>;
343			sleep = <&pmc 0x03000000>;
344		};
345
346		sata@18000 {
347			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
348			reg = <0x18000 0x1000>;
349			interrupts = <44 0x8>;
350			interrupt-parent = <&ipic>;
351			sleep = <&pmc 0x000000c0>;
352		};
353
354		sata@19000 {
355			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
356			reg = <0x19000 0x1000>;
357			interrupts = <45 0x8>;
358			interrupt-parent = <&ipic>;
359			sleep = <&pmc 0x00000030>;
360		};
361
362		/* IPIC
363		 * interrupts cell = <intr #, sense>
364		 * sense values match linux IORESOURCE_IRQ_* defines:
365		 * sense == 8: Level, low assertion
366		 * sense == 2: Edge, high-to-low change
367		 */
368		ipic: interrupt-controller@700 {
369			compatible = "fsl,ipic";
370			interrupt-controller;
371			#address-cells = <0>;
372			#interrupt-cells = <2>;
373			reg = <0x700 0x100>;
374		};
375
376		pmc: power@b00 {
377			compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
378			reg = <0xb00 0x100 0xa00 0x100>;
379			interrupts = <80 0x8>;
380			interrupt-parent = <&ipic>;
381		};
382	};
383
384	pci0: pci@e0008500 {
385		interrupt-map-mask = <0xf800 0 0 7>;
386		interrupt-map = <
387				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
388
389				/* IDSEL AD14 IRQ6 inta */
390				 0x7000 0x0 0x0 0x1 &ipic 22 0x8
391
392				/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
393				 0x7800 0x0 0x0 0x1 &ipic 21 0x8
394				 0x7800 0x0 0x0 0x2 &ipic 22 0x8
395				 0x7800 0x0 0x0 0x4 &ipic 23 0x8
396
397				/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
398				 0xE000 0x0 0x0 0x1 &ipic 23 0x8
399				 0xE000 0x0 0x0 0x2 &ipic 21 0x8
400				 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
401		interrupt-parent = <&ipic>;
402		interrupts = <66 0x8>;
403		bus-range = <0 0>;
404		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
405		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
406		          0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
407		sleep = <&pmc 0x00010000>;
408		clock-frequency = <66666666>;
409		#interrupt-cells = <1>;
410		#size-cells = <2>;
411		#address-cells = <3>;
412		reg = <0xe0008500 0x100		/* internal registers */
413		       0xe0008300 0x8>;		/* config space access registers */
414		compatible = "fsl,mpc8349-pci";
415		device_type = "pci";
416	};
417
418	pci1: pcie@e0009000 {
419		#address-cells = <3>;
420		#size-cells = <2>;
421		#interrupt-cells = <1>;
422		device_type = "pci";
423		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
424		reg = <0xe0009000 0x00001000>;
425		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
426		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
427		bus-range = <0 255>;
428		interrupt-map-mask = <0xf800 0 0 7>;
429		interrupt-map = <0 0 0 1 &ipic 1 8
430				 0 0 0 2 &ipic 1 8
431				 0 0 0 3 &ipic 1 8
432				 0 0 0 4 &ipic 1 8>;
433		sleep = <&pmc 0x00300000>;
434		clock-frequency = <0>;
435
436		pcie@0 {
437			#address-cells = <3>;
438			#size-cells = <2>;
439			device_type = "pci";
440			reg = <0 0 0 0 0>;
441			ranges = <0x02000000 0 0xa8000000
442				  0x02000000 0 0xa8000000
443				  0 0x10000000
444				  0x01000000 0 0x00000000
445				  0x01000000 0 0x00000000
446				  0 0x00800000>;
447		};
448	};
449
450	pci2: pcie@e000a000 {
451		#address-cells = <3>;
452		#size-cells = <2>;
453		#interrupt-cells = <1>;
454		device_type = "pci";
455		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
456		reg = <0xe000a000 0x00001000>;
457		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
458			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
459		bus-range = <0 255>;
460		interrupt-map-mask = <0xf800 0 0 7>;
461		interrupt-map = <0 0 0 1 &ipic 2 8
462				 0 0 0 2 &ipic 2 8
463				 0 0 0 3 &ipic 2 8
464				 0 0 0 4 &ipic 2 8>;
465		sleep = <&pmc 0x000c0000>;
466		clock-frequency = <0>;
467
468		pcie@0 {
469			#address-cells = <3>;
470			#size-cells = <2>;
471			device_type = "pci";
472			reg = <0 0 0 0 0>;
473			ranges = <0x02000000 0 0xc8000000
474				  0x02000000 0 0xc8000000
475				  0 0x10000000
476				  0x01000000 0 0x00000000
477				  0x01000000 0 0x00000000
478				  0 0x00800000>;
479		};
480	};
481};
482