1/* 2 * MPC8349E-mITX-GP Device Tree Source 3 * 4 * Copyright 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "MPC8349EMITXGP"; 16 compatible = "MPC8349EMITXGP", "MPC834xMITX", "MPC83xxMITX"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 serial0 = &serial0; 23 serial1 = &serial1; 24 pci0 = &pci0; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 PowerPC,8349@0 { 32 device_type = "cpu"; 33 reg = <0x0>; 34 d-cache-line-size = <32>; 35 i-cache-line-size = <32>; 36 d-cache-size = <32768>; 37 i-cache-size = <32768>; 38 timebase-frequency = <0>; // from bootloader 39 bus-frequency = <0>; // from bootloader 40 clock-frequency = <0>; // from bootloader 41 }; 42 }; 43 44 memory { 45 device_type = "memory"; 46 reg = <0x00000000 0x10000000>; 47 }; 48 49 soc8349@e0000000 { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 device_type = "soc"; 53 compatible = "simple-bus"; 54 ranges = <0x0 0xe0000000 0x00100000>; 55 reg = <0xe0000000 0x00000200>; 56 bus-frequency = <0>; // from bootloader 57 58 wdt@200 { 59 device_type = "watchdog"; 60 compatible = "mpc83xx_wdt"; 61 reg = <0x200 0x100>; 62 }; 63 64 i2c@3000 { 65 #address-cells = <1>; 66 #size-cells = <0>; 67 cell-index = <0>; 68 compatible = "fsl-i2c"; 69 reg = <0x3000 0x100>; 70 interrupts = <14 0x8>; 71 interrupt-parent = <&ipic>; 72 dfsrr; 73 }; 74 75 i2c@3100 { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 cell-index = <1>; 79 compatible = "fsl-i2c"; 80 reg = <0x3100 0x100>; 81 interrupts = <15 0x8>; 82 interrupt-parent = <&ipic>; 83 dfsrr; 84 }; 85 86 spi@7000 { 87 cell-index = <0>; 88 compatible = "fsl,spi"; 89 reg = <0x7000 0x1000>; 90 interrupts = <16 0x8>; 91 interrupt-parent = <&ipic>; 92 mode = "cpu"; 93 }; 94 95 dma@82a8 { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; 99 reg = <0x82a8 4>; 100 ranges = <0 0x8100 0x1a8>; 101 interrupt-parent = <&ipic>; 102 interrupts = <71 8>; 103 cell-index = <0>; 104 dma-channel@0 { 105 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 106 reg = <0 0x80>; 107 cell-index = <0>; 108 interrupt-parent = <&ipic>; 109 interrupts = <71 8>; 110 }; 111 dma-channel@80 { 112 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 113 reg = <0x80 0x80>; 114 cell-index = <1>; 115 interrupt-parent = <&ipic>; 116 interrupts = <71 8>; 117 }; 118 dma-channel@100 { 119 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 120 reg = <0x100 0x80>; 121 cell-index = <2>; 122 interrupt-parent = <&ipic>; 123 interrupts = <71 8>; 124 }; 125 dma-channel@180 { 126 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 127 reg = <0x180 0x28>; 128 cell-index = <3>; 129 interrupt-parent = <&ipic>; 130 interrupts = <71 8>; 131 }; 132 }; 133 134 usb@23000 { 135 compatible = "fsl-usb2-dr"; 136 reg = <0x23000 0x1000>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 interrupt-parent = <&ipic>; 140 interrupts = <38 0x8>; 141 dr_mode = "otg"; 142 phy_type = "ulpi"; 143 }; 144 145 mdio@24520 { 146 #address-cells = <1>; 147 #size-cells = <0>; 148 compatible = "fsl,gianfar-mdio"; 149 reg = <0x24520 0x20>; 150 151 /* Vitesse 8201 */ 152 phy1c: ethernet-phy@1c { 153 interrupt-parent = <&ipic>; 154 interrupts = <18 0x8>; 155 reg = <0x1c>; 156 device_type = "ethernet-phy"; 157 }; 158 }; 159 160 enet0: ethernet@24000 { 161 cell-index = <0>; 162 device_type = "network"; 163 model = "TSEC"; 164 compatible = "gianfar"; 165 reg = <0x24000 0x1000>; 166 local-mac-address = [ 00 00 00 00 00 00 ]; 167 interrupts = <32 0x8 33 0x8 34 0x8>; 168 interrupt-parent = <&ipic>; 169 phy-handle = <&phy1c>; 170 linux,network-index = <0>; 171 }; 172 173 serial0: serial@4500 { 174 cell-index = <0>; 175 device_type = "serial"; 176 compatible = "ns16550"; 177 reg = <0x4500 0x100>; 178 clock-frequency = <0>; // from bootloader 179 interrupts = <9 0x8>; 180 interrupt-parent = <&ipic>; 181 }; 182 183 serial1: serial@4600 { 184 cell-index = <1>; 185 device_type = "serial"; 186 compatible = "ns16550"; 187 reg = <0x4600 0x100>; 188 clock-frequency = <0>; // from bootloader 189 interrupts = <10 0x8>; 190 interrupt-parent = <&ipic>; 191 }; 192 193 crypto@30000 { 194 compatible = "fsl,sec2.0"; 195 reg = <0x30000 0x10000>; 196 interrupts = <11 0x8>; 197 interrupt-parent = <&ipic>; 198 fsl,num-channels = <4>; 199 fsl,channel-fifo-len = <24>; 200 fsl,exec-units-mask = <0x7e>; 201 fsl,descriptor-types-mask = <0x01010ebf>; 202 }; 203 204 ipic: pic@700 { 205 interrupt-controller; 206 #address-cells = <0>; 207 #interrupt-cells = <2>; 208 reg = <0x700 0x100>; 209 device_type = "ipic"; 210 }; 211 }; 212 213 pci0: pci@e0008600 { 214 cell-index = <2>; 215 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 216 interrupt-map = < 217 /* IDSEL 0x0F - PCI Slot */ 218 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */ 219 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */ 220 >; 221 interrupt-parent = <&ipic>; 222 interrupts = <67 0x8>; 223 bus-range = <0x1 0x1>; 224 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 225 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 226 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>; 227 clock-frequency = <66666666>; 228 #interrupt-cells = <1>; 229 #size-cells = <2>; 230 #address-cells = <3>; 231 reg = <0xe0008600 0x100>; 232 compatible = "fsl,mpc8349-pci"; 233 device_type = "pci"; 234 }; 235}; 236