1/* 2 * MPC8315E RDB Device Tree Source 3 * 4 * Copyright 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 compatible = "fsl,mpc8315erdb"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 ethernet0 = &enet0; 21 ethernet1 = &enet1; 22 serial0 = &serial0; 23 serial1 = &serial1; 24 pci0 = &pci0; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 PowerPC,8315@0 { 32 device_type = "cpu"; 33 reg = <0x0>; 34 d-cache-line-size = <32>; 35 i-cache-line-size = <32>; 36 d-cache-size = <16384>; 37 i-cache-size = <16384>; 38 timebase-frequency = <0>; // from bootloader 39 bus-frequency = <0>; // from bootloader 40 clock-frequency = <0>; // from bootloader 41 }; 42 }; 43 44 memory { 45 device_type = "memory"; 46 reg = <0x00000000 0x08000000>; // 128MB at 0 47 }; 48 49 localbus@e0005000 { 50 #address-cells = <2>; 51 #size-cells = <1>; 52 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; 53 reg = <0xe0005000 0x1000>; 54 interrupts = <77 0x8>; 55 interrupt-parent = <&ipic>; 56 57 // CS0 and CS1 are swapped when 58 // booting from nand, but the 59 // addresses are the same. 60 ranges = <0x0 0x0 0xfe000000 0x00800000 61 0x1 0x0 0xe0600000 0x00002000 62 0x2 0x0 0xf0000000 0x00020000 63 0x3 0x0 0xfa000000 0x00008000>; 64 65 flash@0,0 { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 compatible = "cfi-flash"; 69 reg = <0x0 0x0 0x800000>; 70 bank-width = <2>; 71 device-width = <1>; 72 }; 73 74 nand@1,0 { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 compatible = "fsl,mpc8315-fcm-nand", 78 "fsl,elbc-fcm-nand"; 79 reg = <0x1 0x0 0x2000>; 80 81 u-boot@0 { 82 reg = <0x0 0x100000>; 83 read-only; 84 }; 85 86 kernel@100000 { 87 reg = <0x100000 0x300000>; 88 }; 89 fs@400000 { 90 reg = <0x400000 0x1c00000>; 91 }; 92 }; 93 }; 94 95 immr@e0000000 { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 device_type = "soc"; 99 compatible = "fsl,mpc8315-immr", "simple-bus"; 100 ranges = <0 0xe0000000 0x00100000>; 101 reg = <0xe0000000 0x00000200>; 102 bus-frequency = <0>; 103 104 wdt@200 { 105 device_type = "watchdog"; 106 compatible = "mpc83xx_wdt"; 107 reg = <0x200 0x100>; 108 }; 109 110 i2c@3000 { 111 #address-cells = <1>; 112 #size-cells = <0>; 113 cell-index = <0>; 114 compatible = "fsl-i2c"; 115 reg = <0x3000 0x100>; 116 interrupts = <14 0x8>; 117 interrupt-parent = <&ipic>; 118 dfsrr; 119 rtc@68 { 120 device_type = "rtc"; 121 compatible = "dallas,ds1339"; 122 reg = <0x68>; 123 }; 124 }; 125 126 spi@7000 { 127 cell-index = <0>; 128 compatible = "fsl,spi"; 129 reg = <0x7000 0x1000>; 130 interrupts = <16 0x8>; 131 interrupt-parent = <&ipic>; 132 mode = "cpu"; 133 }; 134 135 dma@82a8 { 136 #address-cells = <1>; 137 #size-cells = <1>; 138 compatible = "fsl,mpc8315-dma", "fsl,elo-dma"; 139 reg = <0x82a8 4>; 140 ranges = <0 0x8100 0x1a8>; 141 interrupt-parent = <&ipic>; 142 interrupts = <71 8>; 143 cell-index = <0>; 144 dma-channel@0 { 145 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 146 reg = <0 0x80>; 147 cell-index = <0>; 148 interrupt-parent = <&ipic>; 149 interrupts = <71 8>; 150 }; 151 dma-channel@80 { 152 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 153 reg = <0x80 0x80>; 154 cell-index = <1>; 155 interrupt-parent = <&ipic>; 156 interrupts = <71 8>; 157 }; 158 dma-channel@100 { 159 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 160 reg = <0x100 0x80>; 161 cell-index = <2>; 162 interrupt-parent = <&ipic>; 163 interrupts = <71 8>; 164 }; 165 dma-channel@180 { 166 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 167 reg = <0x180 0x28>; 168 cell-index = <3>; 169 interrupt-parent = <&ipic>; 170 interrupts = <71 8>; 171 }; 172 }; 173 174 usb@23000 { 175 compatible = "fsl-usb2-dr"; 176 reg = <0x23000 0x1000>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 interrupt-parent = <&ipic>; 180 interrupts = <38 0x8>; 181 phy_type = "utmi"; 182 }; 183 184 mdio@24520 { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 compatible = "fsl,gianfar-mdio"; 188 reg = <0x24520 0x20>; 189 phy0: ethernet-phy@0 { 190 interrupt-parent = <&ipic>; 191 interrupts = <20 0x8>; 192 reg = <0x0>; 193 device_type = "ethernet-phy"; 194 }; 195 phy1: ethernet-phy@1 { 196 interrupt-parent = <&ipic>; 197 interrupts = <19 0x8>; 198 reg = <0x1>; 199 device_type = "ethernet-phy"; 200 }; 201 }; 202 203 enet0: ethernet@24000 { 204 cell-index = <0>; 205 device_type = "network"; 206 model = "eTSEC"; 207 compatible = "gianfar"; 208 reg = <0x24000 0x1000>; 209 local-mac-address = [ 00 00 00 00 00 00 ]; 210 interrupts = <32 0x8 33 0x8 34 0x8>; 211 interrupt-parent = <&ipic>; 212 phy-handle = < &phy0 >; 213 }; 214 215 enet1: ethernet@25000 { 216 cell-index = <1>; 217 device_type = "network"; 218 model = "eTSEC"; 219 compatible = "gianfar"; 220 reg = <0x25000 0x1000>; 221 local-mac-address = [ 00 00 00 00 00 00 ]; 222 interrupts = <35 0x8 36 0x8 37 0x8>; 223 interrupt-parent = <&ipic>; 224 phy-handle = < &phy1 >; 225 }; 226 227 serial0: serial@4500 { 228 cell-index = <0>; 229 device_type = "serial"; 230 compatible = "ns16550"; 231 reg = <0x4500 0x100>; 232 clock-frequency = <0>; 233 interrupts = <9 0x8>; 234 interrupt-parent = <&ipic>; 235 }; 236 237 serial1: serial@4600 { 238 cell-index = <1>; 239 device_type = "serial"; 240 compatible = "ns16550"; 241 reg = <0x4600 0x100>; 242 clock-frequency = <0>; 243 interrupts = <10 0x8>; 244 interrupt-parent = <&ipic>; 245 }; 246 247 crypto@30000 { 248 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", 249 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", 250 "fsl,sec2.0"; 251 reg = <0x30000 0x10000>; 252 interrupts = <11 0x8>; 253 interrupt-parent = <&ipic>; 254 fsl,num-channels = <4>; 255 fsl,channel-fifo-len = <24>; 256 fsl,exec-units-mask = <0x97c>; 257 fsl,descriptor-types-mask = <0x3ab0abf>; 258 }; 259 260 sata@18000 { 261 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 262 reg = <0x18000 0x1000>; 263 cell-index = <1>; 264 interrupts = <44 0x8>; 265 interrupt-parent = <&ipic>; 266 }; 267 268 sata@19000 { 269 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 270 reg = <0x19000 0x1000>; 271 cell-index = <2>; 272 interrupts = <45 0x8>; 273 interrupt-parent = <&ipic>; 274 }; 275 276 /* IPIC 277 * interrupts cell = <intr #, sense> 278 * sense values match linux IORESOURCE_IRQ_* defines: 279 * sense == 8: Level, low assertion 280 * sense == 2: Edge, high-to-low change 281 */ 282 ipic: interrupt-controller@700 { 283 interrupt-controller; 284 #address-cells = <0>; 285 #interrupt-cells = <2>; 286 reg = <0x700 0x100>; 287 device_type = "ipic"; 288 }; 289 }; 290 291 pci0: pci@e0008500 { 292 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 293 interrupt-map = < 294 /* IDSEL 0x0E -mini PCI */ 295 0x7000 0x0 0x0 0x1 &ipic 18 0x8 296 0x7000 0x0 0x0 0x2 &ipic 18 0x8 297 0x7000 0x0 0x0 0x3 &ipic 18 0x8 298 0x7000 0x0 0x0 0x4 &ipic 18 0x8 299 300 /* IDSEL 0x0F -mini PCI */ 301 0x7800 0x0 0x0 0x1 &ipic 17 0x8 302 0x7800 0x0 0x0 0x2 &ipic 17 0x8 303 0x7800 0x0 0x0 0x3 &ipic 17 0x8 304 0x7800 0x0 0x0 0x4 &ipic 17 0x8 305 306 /* IDSEL 0x10 - PCI slot */ 307 0x8000 0x0 0x0 0x1 &ipic 48 0x8 308 0x8000 0x0 0x0 0x2 &ipic 17 0x8 309 0x8000 0x0 0x0 0x3 &ipic 48 0x8 310 0x8000 0x0 0x0 0x4 &ipic 17 0x8>; 311 interrupt-parent = <&ipic>; 312 interrupts = <66 0x8>; 313 bus-range = <0x0 0x0>; 314 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 315 0x42000000 0 0x80000000 0x80000000 0 0x10000000 316 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>; 317 clock-frequency = <66666666>; 318 #interrupt-cells = <1>; 319 #size-cells = <2>; 320 #address-cells = <3>; 321 reg = <0xe0008500 0x100 /* internal registers */ 322 0xe0008300 0x8>; /* config space access registers */ 323 compatible = "fsl,mpc8349-pci"; 324 device_type = "pci"; 325 }; 326}; 327