1/*
2 * MPC8315E RDB Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	compatible = "fsl,mpc8315erdb";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		ethernet0 = &enet0;
21		ethernet1 = &enet1;
22		serial0 = &serial0;
23		serial1 = &serial1;
24		pci0 = &pci0;
25		pci1 = &pci1;
26		pci2 = &pci2;
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		PowerPC,8315@0 {
34			device_type = "cpu";
35			reg = <0x0>;
36			d-cache-line-size = <32>;
37			i-cache-line-size = <32>;
38			d-cache-size = <16384>;
39			i-cache-size = <16384>;
40			timebase-frequency = <0>;	// from bootloader
41			bus-frequency = <0>;		// from bootloader
42			clock-frequency = <0>;		// from bootloader
43		};
44	};
45
46	memory {
47		device_type = "memory";
48		reg = <0x00000000 0x08000000>;	// 128MB at 0
49	};
50
51	localbus@e0005000 {
52		#address-cells = <2>;
53		#size-cells = <1>;
54		compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
55		reg = <0xe0005000 0x1000>;
56		interrupts = <77 0x8>;
57		interrupt-parent = <&ipic>;
58
59		// CS0 and CS1 are swapped when
60		// booting from nand, but the
61		// addresses are the same.
62		ranges = <0x0 0x0 0xfe000000 0x00800000
63		          0x1 0x0 0xe0600000 0x00002000
64		          0x2 0x0 0xf0000000 0x00020000
65		          0x3 0x0 0xfa000000 0x00008000>;
66
67		flash@0,0 {
68			#address-cells = <1>;
69			#size-cells = <1>;
70			compatible = "cfi-flash";
71			reg = <0x0 0x0 0x800000>;
72			bank-width = <2>;
73			device-width = <1>;
74		};
75
76		nand@1,0 {
77			#address-cells = <1>;
78			#size-cells = <1>;
79			compatible = "fsl,mpc8315-fcm-nand",
80			             "fsl,elbc-fcm-nand";
81			reg = <0x1 0x0 0x2000>;
82
83			u-boot@0 {
84				reg = <0x0 0x100000>;
85				read-only;
86			};
87
88			kernel@100000 {
89				reg = <0x100000 0x300000>;
90			};
91			fs@400000 {
92				reg = <0x400000 0x1c00000>;
93			};
94		};
95	};
96
97	immr@e0000000 {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		device_type = "soc";
101		compatible = "fsl,mpc8315-immr", "simple-bus";
102		ranges = <0 0xe0000000 0x00100000>;
103		reg = <0xe0000000 0x00000200>;
104		bus-frequency = <0>;
105
106		wdt@200 {
107			device_type = "watchdog";
108			compatible = "mpc83xx_wdt";
109			reg = <0x200 0x100>;
110		};
111
112		i2c@3000 {
113			#address-cells = <1>;
114			#size-cells = <0>;
115			cell-index = <0>;
116			compatible = "fsl-i2c";
117			reg = <0x3000 0x100>;
118			interrupts = <14 0x8>;
119			interrupt-parent = <&ipic>;
120			dfsrr;
121			rtc@68 {
122				compatible = "dallas,ds1339";
123				reg = <0x68>;
124			};
125
126			mcu_pio: mcu@a {
127				#gpio-cells = <2>;
128				compatible = "fsl,mc9s08qg8-mpc8315erdb",
129					     "fsl,mcu-mpc8349emitx";
130				reg = <0x0a>;
131				gpio-controller;
132			};
133		};
134
135		spi@7000 {
136			cell-index = <0>;
137			compatible = "fsl,spi";
138			reg = <0x7000 0x1000>;
139			interrupts = <16 0x8>;
140			interrupt-parent = <&ipic>;
141			mode = "cpu";
142		};
143
144		dma@82a8 {
145			#address-cells = <1>;
146			#size-cells = <1>;
147			compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
148			reg = <0x82a8 4>;
149			ranges = <0 0x8100 0x1a8>;
150			interrupt-parent = <&ipic>;
151			interrupts = <71 8>;
152			cell-index = <0>;
153			dma-channel@0 {
154				compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
155				reg = <0 0x80>;
156				cell-index = <0>;
157				interrupt-parent = <&ipic>;
158				interrupts = <71 8>;
159			};
160			dma-channel@80 {
161				compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
162				reg = <0x80 0x80>;
163				cell-index = <1>;
164				interrupt-parent = <&ipic>;
165				interrupts = <71 8>;
166			};
167			dma-channel@100 {
168				compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
169				reg = <0x100 0x80>;
170				cell-index = <2>;
171				interrupt-parent = <&ipic>;
172				interrupts = <71 8>;
173			};
174			dma-channel@180 {
175				compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
176				reg = <0x180 0x28>;
177				cell-index = <3>;
178				interrupt-parent = <&ipic>;
179				interrupts = <71 8>;
180			};
181		};
182
183		usb@23000 {
184			compatible = "fsl-usb2-dr";
185			reg = <0x23000 0x1000>;
186			#address-cells = <1>;
187			#size-cells = <0>;
188			interrupt-parent = <&ipic>;
189			interrupts = <38 0x8>;
190			phy_type = "utmi";
191		};
192
193		enet0: ethernet@24000 {
194			#address-cells = <1>;
195			#size-cells = <1>;
196			cell-index = <0>;
197			device_type = "network";
198			model = "eTSEC";
199			compatible = "gianfar";
200			reg = <0x24000 0x1000>;
201			ranges = <0x0 0x24000 0x1000>;
202			local-mac-address = [ 00 00 00 00 00 00 ];
203			interrupts = <32 0x8 33 0x8 34 0x8>;
204			interrupt-parent = <&ipic>;
205			tbi-handle = <&tbi0>;
206			phy-handle = < &phy0 >;
207			fsl,magic-packet;
208
209			mdio@520 {
210				#address-cells = <1>;
211				#size-cells = <0>;
212				compatible = "fsl,gianfar-mdio";
213				reg = <0x520 0x20>;
214
215				phy0: ethernet-phy@0 {
216					interrupt-parent = <&ipic>;
217					interrupts = <20 0x8>;
218					reg = <0x0>;
219					device_type = "ethernet-phy";
220				};
221
222				phy1: ethernet-phy@1 {
223					interrupt-parent = <&ipic>;
224					interrupts = <19 0x8>;
225					reg = <0x1>;
226					device_type = "ethernet-phy";
227				};
228
229				tbi0: tbi-phy@11 {
230					reg = <0x11>;
231					device_type = "tbi-phy";
232				};
233			};
234		};
235
236		enet1: ethernet@25000 {
237			#address-cells = <1>;
238			#size-cells = <1>;
239			cell-index = <1>;
240			device_type = "network";
241			model = "eTSEC";
242			compatible = "gianfar";
243			reg = <0x25000 0x1000>;
244			ranges = <0x0 0x25000 0x1000>;
245			local-mac-address = [ 00 00 00 00 00 00 ];
246			interrupts = <35 0x8 36 0x8 37 0x8>;
247			interrupt-parent = <&ipic>;
248			tbi-handle = <&tbi1>;
249			phy-handle = < &phy1 >;
250			fsl,magic-packet;
251
252			mdio@520 {
253				#address-cells = <1>;
254				#size-cells = <0>;
255				compatible = "fsl,gianfar-tbi";
256				reg = <0x520 0x20>;
257
258				tbi1: tbi-phy@11 {
259					reg = <0x11>;
260					device_type = "tbi-phy";
261				};
262			};
263		};
264
265		serial0: serial@4500 {
266			cell-index = <0>;
267			device_type = "serial";
268			compatible = "ns16550";
269			reg = <0x4500 0x100>;
270			clock-frequency = <133333333>;
271			interrupts = <9 0x8>;
272			interrupt-parent = <&ipic>;
273		};
274
275		serial1: serial@4600 {
276			cell-index = <1>;
277			device_type = "serial";
278			compatible = "ns16550";
279			reg = <0x4600 0x100>;
280			clock-frequency = <133333333>;
281			interrupts = <10 0x8>;
282			interrupt-parent = <&ipic>;
283		};
284
285		crypto@30000 {
286			compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
287				     "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
288				     "fsl,sec2.0";
289			reg = <0x30000 0x10000>;
290			interrupts = <11 0x8>;
291			interrupt-parent = <&ipic>;
292			fsl,num-channels = <4>;
293			fsl,channel-fifo-len = <24>;
294			fsl,exec-units-mask = <0x97c>;
295			fsl,descriptor-types-mask = <0x3a30abf>;
296		};
297
298		sata@18000 {
299			compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
300			reg = <0x18000 0x1000>;
301			cell-index = <1>;
302			interrupts = <44 0x8>;
303			interrupt-parent = <&ipic>;
304		};
305
306		sata@19000 {
307			compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
308			reg = <0x19000 0x1000>;
309			cell-index = <2>;
310			interrupts = <45 0x8>;
311			interrupt-parent = <&ipic>;
312		};
313
314		gtm1: timer@500 {
315			compatible = "fsl,mpc8315-gtm", "fsl,gtm";
316			reg = <0x500 0x100>;
317			interrupts = <90 8 78 8 84 8 72 8>;
318			interrupt-parent = <&ipic>;
319			clock-frequency = <133333333>;
320		};
321
322		timer@600 {
323			compatible = "fsl,mpc8315-gtm", "fsl,gtm";
324			reg = <0x600 0x100>;
325			interrupts = <91 8 79 8 85 8 73 8>;
326			interrupt-parent = <&ipic>;
327			clock-frequency = <133333333>;
328		};
329
330		/* IPIC
331		 * interrupts cell = <intr #, sense>
332		 * sense values match linux IORESOURCE_IRQ_* defines:
333		 * sense == 8: Level, low assertion
334		 * sense == 2: Edge, high-to-low change
335		 */
336		ipic: interrupt-controller@700 {
337			interrupt-controller;
338			#address-cells = <0>;
339			#interrupt-cells = <2>;
340			reg = <0x700 0x100>;
341			device_type = "ipic";
342		};
343
344		ipic-msi@7c0 {
345			compatible = "fsl,ipic-msi";
346			reg = <0x7c0 0x40>;
347			msi-available-ranges = <0 0x100>;
348			interrupts = <0x43 0x8
349				      0x4  0x8
350				      0x51 0x8
351				      0x52 0x8
352				      0x56 0x8
353				      0x57 0x8
354				      0x58 0x8
355				      0x59 0x8>;
356			interrupt-parent = < &ipic >;
357		};
358
359		pmc: power@b00 {
360			compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
361				     "fsl,mpc8349-pmc";
362			reg = <0xb00 0x100 0xa00 0x100>;
363			interrupts = <80 8>;
364			interrupt-parent = <&ipic>;
365			fsl,mpc8313-wakeup-timer = <&gtm1>;
366		};
367	};
368
369	pci0: pci@e0008500 {
370		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
371		interrupt-map = <
372				/* IDSEL 0x0E -mini PCI */
373				 0x7000 0x0 0x0 0x1 &ipic 18 0x8
374				 0x7000 0x0 0x0 0x2 &ipic 18 0x8
375				 0x7000 0x0 0x0 0x3 &ipic 18 0x8
376				 0x7000 0x0 0x0 0x4 &ipic 18 0x8
377
378				/* IDSEL 0x0F -mini PCI */
379				 0x7800 0x0 0x0 0x1 &ipic 17 0x8
380				 0x7800 0x0 0x0 0x2 &ipic 17 0x8
381				 0x7800 0x0 0x0 0x3 &ipic 17 0x8
382				 0x7800 0x0 0x0 0x4 &ipic 17 0x8
383
384				/* IDSEL 0x10 - PCI slot */
385				 0x8000 0x0 0x0 0x1 &ipic 48 0x8
386				 0x8000 0x0 0x0 0x2 &ipic 17 0x8
387				 0x8000 0x0 0x0 0x3 &ipic 48 0x8
388				 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
389		interrupt-parent = <&ipic>;
390		interrupts = <66 0x8>;
391		bus-range = <0x0 0x0>;
392		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
393			  0x42000000 0 0x80000000 0x80000000 0 0x10000000
394			  0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
395		clock-frequency = <66666666>;
396		#interrupt-cells = <1>;
397		#size-cells = <2>;
398		#address-cells = <3>;
399		reg = <0xe0008500 0x100		/* internal registers */
400		       0xe0008300 0x8>;		/* config space access registers */
401		compatible = "fsl,mpc8349-pci";
402		device_type = "pci";
403	};
404
405	pci1: pcie@e0009000 {
406		#address-cells = <3>;
407		#size-cells = <2>;
408		#interrupt-cells = <1>;
409		device_type = "pci";
410		compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
411		reg = <0xe0009000 0x00001000>;
412		ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
413		          0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
414		bus-range = <0 255>;
415		interrupt-map-mask = <0xf800 0 0 7>;
416		interrupt-map = <0 0 0 1 &ipic 1 8
417				 0 0 0 2 &ipic 1 8
418				 0 0 0 3 &ipic 1 8
419				 0 0 0 4 &ipic 1 8>;
420		clock-frequency = <0>;
421
422		pcie@0 {
423			#address-cells = <3>;
424			#size-cells = <2>;
425			device_type = "pci";
426			reg = <0 0 0 0 0>;
427			ranges = <0x02000000 0 0xa0000000
428				  0x02000000 0 0xa0000000
429				  0 0x10000000
430				  0x01000000 0 0x00000000
431				  0x01000000 0 0x00000000
432				  0 0x00800000>;
433		};
434	};
435
436	pci2: pcie@e000a000 {
437		#address-cells = <3>;
438		#size-cells = <2>;
439		#interrupt-cells = <1>;
440		device_type = "pci";
441		compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
442		reg = <0xe000a000 0x00001000>;
443		ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
444			  0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
445		bus-range = <0 255>;
446		interrupt-map-mask = <0xf800 0 0 7>;
447		interrupt-map = <0 0 0 1 &ipic 2 8
448				 0 0 0 2 &ipic 2 8
449				 0 0 0 3 &ipic 2 8
450				 0 0 0 4 &ipic 2 8>;
451		clock-frequency = <0>;
452
453		pcie@0 {
454			#address-cells = <3>;
455			#size-cells = <2>;
456			device_type = "pci";
457			reg = <0 0 0 0 0>;
458			ranges = <0x02000000 0 0xc0000000
459				  0x02000000 0 0xc0000000
460				  0 0x10000000
461				  0x01000000 0 0x00000000
462				  0x01000000 0 0x00000000
463				  0 0x00800000>;
464		};
465	};
466
467	leds {
468		compatible = "gpio-leds";
469
470		pwr {
471			gpios = <&mcu_pio 0 0>;
472			default-state = "on";
473		};
474
475		hdd {
476			gpios = <&mcu_pio 1 0>;
477			linux,default-trigger = "ide-disk";
478		};
479	};
480};
481