1/*
2 * MPC8315E RDB Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	compatible = "fsl,mpc8315erdb";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		ethernet0 = &enet0;
21		ethernet1 = &enet1;
22		serial0 = &serial0;
23		serial1 = &serial1;
24		pci0 = &pci0;
25		pci1 = &pci1;
26		pci2 = &pci2;
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		PowerPC,8315@0 {
34			device_type = "cpu";
35			reg = <0x0>;
36			d-cache-line-size = <32>;
37			i-cache-line-size = <32>;
38			d-cache-size = <16384>;
39			i-cache-size = <16384>;
40			timebase-frequency = <0>;	// from bootloader
41			bus-frequency = <0>;		// from bootloader
42			clock-frequency = <0>;		// from bootloader
43		};
44	};
45
46	memory {
47		device_type = "memory";
48		reg = <0x00000000 0x08000000>;	// 128MB at 0
49	};
50
51	localbus@e0005000 {
52		#address-cells = <2>;
53		#size-cells = <1>;
54		compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
55		reg = <0xe0005000 0x1000>;
56		interrupts = <77 0x8>;
57		interrupt-parent = <&ipic>;
58
59		// CS0 and CS1 are swapped when
60		// booting from nand, but the
61		// addresses are the same.
62		ranges = <0x0 0x0 0xfe000000 0x00800000
63		          0x1 0x0 0xe0600000 0x00002000
64		          0x2 0x0 0xf0000000 0x00020000
65		          0x3 0x0 0xfa000000 0x00008000>;
66
67		flash@0,0 {
68			#address-cells = <1>;
69			#size-cells = <1>;
70			compatible = "cfi-flash";
71			reg = <0x0 0x0 0x800000>;
72			bank-width = <2>;
73			device-width = <1>;
74		};
75
76		nand@1,0 {
77			#address-cells = <1>;
78			#size-cells = <1>;
79			compatible = "fsl,mpc8315-fcm-nand",
80			             "fsl,elbc-fcm-nand";
81			reg = <0x1 0x0 0x2000>;
82
83			u-boot@0 {
84				reg = <0x0 0x100000>;
85				read-only;
86			};
87
88			kernel@100000 {
89				reg = <0x100000 0x300000>;
90			};
91			fs@400000 {
92				reg = <0x400000 0x1c00000>;
93			};
94		};
95	};
96
97	immr@e0000000 {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		device_type = "soc";
101		compatible = "fsl,mpc8315-immr", "simple-bus";
102		ranges = <0 0xe0000000 0x00100000>;
103		reg = <0xe0000000 0x00000200>;
104		bus-frequency = <0>;
105
106		wdt@200 {
107			device_type = "watchdog";
108			compatible = "mpc83xx_wdt";
109			reg = <0x200 0x100>;
110		};
111
112		i2c@3000 {
113			#address-cells = <1>;
114			#size-cells = <0>;
115			cell-index = <0>;
116			compatible = "fsl-i2c";
117			reg = <0x3000 0x100>;
118			interrupts = <14 0x8>;
119			interrupt-parent = <&ipic>;
120			dfsrr;
121			rtc@68 {
122				compatible = "dallas,ds1339";
123				reg = <0x68>;
124			};
125
126			mcu_pio: mcu@a {
127				#gpio-cells = <2>;
128				compatible = "fsl,mc9s08qg8-mpc8315erdb",
129					     "fsl,mcu-mpc8349emitx";
130				reg = <0x0a>;
131				gpio-controller;
132			};
133		};
134
135		spi@7000 {
136			cell-index = <0>;
137			compatible = "fsl,spi";
138			reg = <0x7000 0x1000>;
139			interrupts = <16 0x8>;
140			interrupt-parent = <&ipic>;
141			mode = "cpu";
142		};
143
144		dma@82a8 {
145			#address-cells = <1>;
146			#size-cells = <1>;
147			compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
148			reg = <0x82a8 4>;
149			ranges = <0 0x8100 0x1a8>;
150			interrupt-parent = <&ipic>;
151			interrupts = <71 8>;
152			cell-index = <0>;
153			dma-channel@0 {
154				compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
155				reg = <0 0x80>;
156				cell-index = <0>;
157				interrupt-parent = <&ipic>;
158				interrupts = <71 8>;
159			};
160			dma-channel@80 {
161				compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
162				reg = <0x80 0x80>;
163				cell-index = <1>;
164				interrupt-parent = <&ipic>;
165				interrupts = <71 8>;
166			};
167			dma-channel@100 {
168				compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
169				reg = <0x100 0x80>;
170				cell-index = <2>;
171				interrupt-parent = <&ipic>;
172				interrupts = <71 8>;
173			};
174			dma-channel@180 {
175				compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
176				reg = <0x180 0x28>;
177				cell-index = <3>;
178				interrupt-parent = <&ipic>;
179				interrupts = <71 8>;
180			};
181		};
182
183		usb@23000 {
184			compatible = "fsl-usb2-dr";
185			reg = <0x23000 0x1000>;
186			#address-cells = <1>;
187			#size-cells = <0>;
188			interrupt-parent = <&ipic>;
189			interrupts = <38 0x8>;
190			phy_type = "utmi";
191		};
192
193		mdio@24520 {
194			#address-cells = <1>;
195			#size-cells = <0>;
196			compatible = "fsl,gianfar-mdio";
197			reg = <0x24520 0x20>;
198			phy0: ethernet-phy@0 {
199				interrupt-parent = <&ipic>;
200				interrupts = <20 0x8>;
201				reg = <0x0>;
202				device_type = "ethernet-phy";
203			};
204			phy1: ethernet-phy@1 {
205				interrupt-parent = <&ipic>;
206				interrupts = <19 0x8>;
207				reg = <0x1>;
208				device_type = "ethernet-phy";
209			};
210			tbi0: tbi-phy@11 {
211				reg = <0x11>;
212				device_type = "tbi-phy";
213			};
214		};
215
216		mdio@25520 {
217			#address-cells = <1>;
218			#size-cells = <0>;
219			compatible = "fsl,gianfar-tbi";
220			reg = <0x25520 0x20>;
221
222			tbi1: tbi-phy@11 {
223				reg = <0x11>;
224				device_type = "tbi-phy";
225			};
226		};
227
228
229		enet0: ethernet@24000 {
230			cell-index = <0>;
231			device_type = "network";
232			model = "eTSEC";
233			compatible = "gianfar";
234			reg = <0x24000 0x1000>;
235			local-mac-address = [ 00 00 00 00 00 00 ];
236			interrupts = <32 0x8 33 0x8 34 0x8>;
237			interrupt-parent = <&ipic>;
238			tbi-handle = <&tbi0>;
239			phy-handle = < &phy0 >;
240		};
241
242		enet1: ethernet@25000 {
243			cell-index = <1>;
244			device_type = "network";
245			model = "eTSEC";
246			compatible = "gianfar";
247			reg = <0x25000 0x1000>;
248			local-mac-address = [ 00 00 00 00 00 00 ];
249			interrupts = <35 0x8 36 0x8 37 0x8>;
250			interrupt-parent = <&ipic>;
251			tbi-handle = <&tbi1>;
252			phy-handle = < &phy1 >;
253		};
254
255		serial0: serial@4500 {
256			cell-index = <0>;
257			device_type = "serial";
258			compatible = "ns16550";
259			reg = <0x4500 0x100>;
260			clock-frequency = <133333333>;
261			interrupts = <9 0x8>;
262			interrupt-parent = <&ipic>;
263		};
264
265		serial1: serial@4600 {
266			cell-index = <1>;
267			device_type = "serial";
268			compatible = "ns16550";
269			reg = <0x4600 0x100>;
270			clock-frequency = <133333333>;
271			interrupts = <10 0x8>;
272			interrupt-parent = <&ipic>;
273		};
274
275		crypto@30000 {
276			compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
277				     "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
278				     "fsl,sec2.0";
279			reg = <0x30000 0x10000>;
280			interrupts = <11 0x8>;
281			interrupt-parent = <&ipic>;
282			fsl,num-channels = <4>;
283			fsl,channel-fifo-len = <24>;
284			fsl,exec-units-mask = <0x97c>;
285			fsl,descriptor-types-mask = <0x3ab0abf>;
286		};
287
288		sata@18000 {
289			compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
290			reg = <0x18000 0x1000>;
291			cell-index = <1>;
292			interrupts = <44 0x8>;
293			interrupt-parent = <&ipic>;
294		};
295
296		sata@19000 {
297			compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
298			reg = <0x19000 0x1000>;
299			cell-index = <2>;
300			interrupts = <45 0x8>;
301			interrupt-parent = <&ipic>;
302		};
303
304		/* IPIC
305		 * interrupts cell = <intr #, sense>
306		 * sense values match linux IORESOURCE_IRQ_* defines:
307		 * sense == 8: Level, low assertion
308		 * sense == 2: Edge, high-to-low change
309		 */
310		ipic: interrupt-controller@700 {
311			interrupt-controller;
312			#address-cells = <0>;
313			#interrupt-cells = <2>;
314			reg = <0x700 0x100>;
315			device_type = "ipic";
316		};
317	};
318
319	pci0: pci@e0008500 {
320		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
321		interrupt-map = <
322				/* IDSEL 0x0E -mini PCI */
323				 0x7000 0x0 0x0 0x1 &ipic 18 0x8
324				 0x7000 0x0 0x0 0x2 &ipic 18 0x8
325				 0x7000 0x0 0x0 0x3 &ipic 18 0x8
326				 0x7000 0x0 0x0 0x4 &ipic 18 0x8
327
328				/* IDSEL 0x0F -mini PCI */
329				 0x7800 0x0 0x0 0x1 &ipic 17 0x8
330				 0x7800 0x0 0x0 0x2 &ipic 17 0x8
331				 0x7800 0x0 0x0 0x3 &ipic 17 0x8
332				 0x7800 0x0 0x0 0x4 &ipic 17 0x8
333
334				/* IDSEL 0x10 - PCI slot */
335				 0x8000 0x0 0x0 0x1 &ipic 48 0x8
336				 0x8000 0x0 0x0 0x2 &ipic 17 0x8
337				 0x8000 0x0 0x0 0x3 &ipic 48 0x8
338				 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
339		interrupt-parent = <&ipic>;
340		interrupts = <66 0x8>;
341		bus-range = <0x0 0x0>;
342		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
343			  0x42000000 0 0x80000000 0x80000000 0 0x10000000
344			  0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
345		clock-frequency = <66666666>;
346		#interrupt-cells = <1>;
347		#size-cells = <2>;
348		#address-cells = <3>;
349		reg = <0xe0008500 0x100		/* internal registers */
350		       0xe0008300 0x8>;		/* config space access registers */
351		compatible = "fsl,mpc8349-pci";
352		device_type = "pci";
353	};
354
355	pci1: pcie@e0009000 {
356		#address-cells = <3>;
357		#size-cells = <2>;
358		#interrupt-cells = <1>;
359		device_type = "pci";
360		compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
361		reg = <0xe0009000 0x00001000>;
362		ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
363		          0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
364		bus-range = <0 255>;
365		interrupt-map-mask = <0xf800 0 0 7>;
366		interrupt-map = <0 0 0 1 &ipic 1 8
367				 0 0 0 2 &ipic 1 8
368				 0 0 0 3 &ipic 1 8
369				 0 0 0 4 &ipic 1 8>;
370		clock-frequency = <0>;
371
372		pcie@0 {
373			#address-cells = <3>;
374			#size-cells = <2>;
375			device_type = "pci";
376			reg = <0 0 0 0 0>;
377			ranges = <0x02000000 0 0xa0000000
378				  0x02000000 0 0xa0000000
379				  0 0x10000000
380				  0x01000000 0 0x00000000
381				  0x01000000 0 0x00000000
382				  0 0x00800000>;
383		};
384	};
385
386	pci2: pcie@e000a000 {
387		#address-cells = <3>;
388		#size-cells = <2>;
389		#interrupt-cells = <1>;
390		device_type = "pci";
391		compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
392		reg = <0xe000a000 0x00001000>;
393		ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
394			  0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
395		bus-range = <0 255>;
396		interrupt-map-mask = <0xf800 0 0 7>;
397		interrupt-map = <0 0 0 1 &ipic 2 8
398				 0 0 0 2 &ipic 2 8
399				 0 0 0 3 &ipic 2 8
400				 0 0 0 4 &ipic 2 8>;
401		clock-frequency = <0>;
402
403		pcie@0 {
404			#address-cells = <3>;
405			#size-cells = <2>;
406			device_type = "pci";
407			reg = <0 0 0 0 0>;
408			ranges = <0x02000000 0 0xc0000000
409				  0x02000000 0 0xc0000000
410				  0 0x10000000
411				  0x01000000 0 0x00000000
412				  0x01000000 0 0x00000000
413				  0 0x00800000>;
414		};
415	};
416};
417