1/* 2 * base MPC5121 Device Tree Source 3 * 4 * Copyright 2007-2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12#include <dt-bindings/clock/mpc512x-clock.h> 13 14/dts-v1/; 15 16/ { 17 model = "mpc5121"; 18 compatible = "fsl,mpc5121"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 interrupt-parent = <&ipic>; 22 23 aliases { 24 ethernet0 = ð0; 25 pci = &pci; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 PowerPC,5121@0 { 33 device_type = "cpu"; 34 reg = <0>; 35 d-cache-line-size = <0x20>; /* 32 bytes */ 36 i-cache-line-size = <0x20>; /* 32 bytes */ 37 d-cache-size = <0x8000>; /* L1, 32K */ 38 i-cache-size = <0x8000>; /* L1, 32K */ 39 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */ 40 bus-frequency = <198000000>; /* 198 MHz csb bus */ 41 clock-frequency = <396000000>; /* 396 MHz ppc core */ 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <0x00000000 0x10000000>; /* 256MB at 0 */ 48 }; 49 50 mbx@20000000 { 51 compatible = "fsl,mpc5121-mbx"; 52 reg = <0x20000000 0x4000>; 53 interrupts = <66 0x8>; 54 clocks = <&clks MPC512x_CLK_MBX_BUS>, 55 <&clks MPC512x_CLK_MBX_3D>, 56 <&clks MPC512x_CLK_MBX>; 57 clock-names = "mbx-bus", "mbx-3d", "mbx"; 58 }; 59 60 sram@30000000 { 61 compatible = "fsl,mpc5121-sram"; 62 reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */ 63 }; 64 65 nfc@40000000 { 66 compatible = "fsl,mpc5121-nfc"; 67 reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */ 68 interrupts = <6 8>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 clocks = <&clks MPC512x_CLK_NFC>; 72 clock-names = "ipg"; 73 }; 74 75 localbus@80000020 { 76 compatible = "fsl,mpc5121-localbus"; 77 #address-cells = <2>; 78 #size-cells = <1>; 79 reg = <0x80000020 0x40>; 80 ranges = <0x0 0x0 0xfc000000 0x04000000>; 81 }; 82 83 clocks { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 87 osc: osc { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <33000000>; 91 }; 92 }; 93 94 soc@80000000 { 95 compatible = "fsl,mpc5121-immr"; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges = <0x0 0x80000000 0x400000>; 99 reg = <0x80000000 0x400000>; 100 bus-frequency = <66000000>; /* 66 MHz ips bus */ 101 102 103 /* 104 * IPIC 105 * interrupts cell = <intr #, sense> 106 * sense values match linux IORESOURCE_IRQ_* defines: 107 * sense == 8: Level, low assertion 108 * sense == 2: Edge, high-to-low change 109 */ 110 ipic: interrupt-controller@c00 { 111 compatible = "fsl,mpc5121-ipic", "fsl,ipic"; 112 interrupt-controller; 113 #address-cells = <0>; 114 #interrupt-cells = <2>; 115 reg = <0xc00 0x100>; 116 }; 117 118 /* Watchdog timer */ 119 wdt@900 { 120 compatible = "fsl,mpc5121-wdt"; 121 reg = <0x900 0x100>; 122 }; 123 124 /* Real time clock */ 125 rtc@a00 { 126 compatible = "fsl,mpc5121-rtc"; 127 reg = <0xa00 0x100>; 128 interrupts = <79 0x8 80 0x8>; 129 }; 130 131 /* Reset module */ 132 reset@e00 { 133 compatible = "fsl,mpc5121-reset"; 134 reg = <0xe00 0x100>; 135 }; 136 137 /* Clock control */ 138 clks: clock@f00 { 139 compatible = "fsl,mpc5121-clock"; 140 reg = <0xf00 0x100>; 141 #clock-cells = <1>; 142 clocks = <&osc>; 143 clock-names = "osc"; 144 }; 145 146 /* Power Management Controller */ 147 pmc@1000{ 148 compatible = "fsl,mpc5121-pmc"; 149 reg = <0x1000 0x100>; 150 interrupts = <83 0x8>; 151 }; 152 153 gpio@1100 { 154 compatible = "fsl,mpc5121-gpio"; 155 reg = <0x1100 0x100>; 156 interrupts = <78 0x8>; 157 }; 158 159 can@1300 { 160 compatible = "fsl,mpc5121-mscan"; 161 reg = <0x1300 0x80>; 162 interrupts = <12 0x8>; 163 clocks = <&clks MPC512x_CLK_BDLC>, 164 <&clks MPC512x_CLK_IPS>, 165 <&clks MPC512x_CLK_SYS>, 166 <&clks MPC512x_CLK_REF>, 167 <&clks MPC512x_CLK_MSCAN0_MCLK>; 168 clock-names = "ipg", "ips", "sys", "ref", "mclk"; 169 }; 170 171 can@1380 { 172 compatible = "fsl,mpc5121-mscan"; 173 reg = <0x1380 0x80>; 174 interrupts = <13 0x8>; 175 clocks = <&clks MPC512x_CLK_BDLC>, 176 <&clks MPC512x_CLK_IPS>, 177 <&clks MPC512x_CLK_SYS>, 178 <&clks MPC512x_CLK_REF>, 179 <&clks MPC512x_CLK_MSCAN1_MCLK>; 180 clock-names = "ipg", "ips", "sys", "ref", "mclk"; 181 }; 182 183 sdhc@1500 { 184 compatible = "fsl,mpc5121-sdhc"; 185 reg = <0x1500 0x100>; 186 interrupts = <8 0x8>; 187 dmas = <&dma0 30>; 188 dma-names = "rx-tx"; 189 clocks = <&clks MPC512x_CLK_IPS>, 190 <&clks MPC512x_CLK_SDHC>; 191 clock-names = "ipg", "per"; 192 }; 193 194 i2c@1700 { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 198 reg = <0x1700 0x20>; 199 interrupts = <9 0x8>; 200 clocks = <&clks MPC512x_CLK_I2C>; 201 clock-names = "ipg"; 202 }; 203 204 i2c@1720 { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 208 reg = <0x1720 0x20>; 209 interrupts = <10 0x8>; 210 clocks = <&clks MPC512x_CLK_I2C>; 211 clock-names = "ipg"; 212 }; 213 214 i2c@1740 { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 218 reg = <0x1740 0x20>; 219 interrupts = <11 0x8>; 220 clocks = <&clks MPC512x_CLK_I2C>; 221 clock-names = "ipg"; 222 }; 223 224 i2ccontrol@1760 { 225 compatible = "fsl,mpc5121-i2c-ctrl"; 226 reg = <0x1760 0x8>; 227 }; 228 229 axe@2000 { 230 compatible = "fsl,mpc5121-axe"; 231 reg = <0x2000 0x100>; 232 interrupts = <42 0x8>; 233 clocks = <&clks MPC512x_CLK_AXE>; 234 clock-names = "ipg"; 235 }; 236 237 display@2100 { 238 compatible = "fsl,mpc5121-diu"; 239 reg = <0x2100 0x100>; 240 interrupts = <64 0x8>; 241 clocks = <&clks MPC512x_CLK_DIU>; 242 clock-names = "ipg"; 243 }; 244 245 can@2300 { 246 compatible = "fsl,mpc5121-mscan"; 247 reg = <0x2300 0x80>; 248 interrupts = <90 0x8>; 249 clocks = <&clks MPC512x_CLK_BDLC>, 250 <&clks MPC512x_CLK_IPS>, 251 <&clks MPC512x_CLK_SYS>, 252 <&clks MPC512x_CLK_REF>, 253 <&clks MPC512x_CLK_MSCAN2_MCLK>; 254 clock-names = "ipg", "ips", "sys", "ref", "mclk"; 255 }; 256 257 can@2380 { 258 compatible = "fsl,mpc5121-mscan"; 259 reg = <0x2380 0x80>; 260 interrupts = <91 0x8>; 261 clocks = <&clks MPC512x_CLK_BDLC>, 262 <&clks MPC512x_CLK_IPS>, 263 <&clks MPC512x_CLK_SYS>, 264 <&clks MPC512x_CLK_REF>, 265 <&clks MPC512x_CLK_MSCAN3_MCLK>; 266 clock-names = "ipg", "ips", "sys", "ref", "mclk"; 267 }; 268 269 viu@2400 { 270 compatible = "fsl,mpc5121-viu"; 271 reg = <0x2400 0x400>; 272 interrupts = <67 0x8>; 273 clocks = <&clks MPC512x_CLK_VIU>; 274 clock-names = "ipg"; 275 }; 276 277 mdio@2800 { 278 compatible = "fsl,mpc5121-fec-mdio"; 279 reg = <0x2800 0x800>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 clocks = <&clks MPC512x_CLK_FEC>; 283 clock-names = "per"; 284 }; 285 286 eth0: ethernet@2800 { 287 device_type = "network"; 288 compatible = "fsl,mpc5121-fec"; 289 reg = <0x2800 0x800>; 290 local-mac-address = [ 00 00 00 00 00 00 ]; 291 interrupts = <4 0x8>; 292 clocks = <&clks MPC512x_CLK_FEC>; 293 clock-names = "per"; 294 }; 295 296 /* USB1 using external ULPI PHY */ 297 usb@3000 { 298 compatible = "fsl,mpc5121-usb2-dr"; 299 reg = <0x3000 0x600>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 interrupts = <43 0x8>; 303 dr_mode = "otg"; 304 phy_type = "ulpi"; 305 clocks = <&clks MPC512x_CLK_USB1>; 306 clock-names = "ipg"; 307 }; 308 309 /* USB0 using internal UTMI PHY */ 310 usb@4000 { 311 compatible = "fsl,mpc5121-usb2-dr"; 312 reg = <0x4000 0x600>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 interrupts = <44 0x8>; 316 dr_mode = "otg"; 317 phy_type = "utmi_wide"; 318 clocks = <&clks MPC512x_CLK_USB2>; 319 clock-names = "ipg"; 320 }; 321 322 /* IO control */ 323 ioctl@a000 { 324 compatible = "fsl,mpc5121-ioctl"; 325 reg = <0xA000 0x1000>; 326 }; 327 328 /* LocalPlus controller */ 329 lpc@10000 { 330 compatible = "fsl,mpc5121-lpc"; 331 reg = <0x10000 0x100>; 332 }; 333 334 sclpc@10100 { 335 compatible = "fsl,mpc512x-lpbfifo"; 336 reg = <0x10100 0x50>; 337 interrupts = <7 0x8>; 338 dmas = <&dma0 26>; 339 dma-names = "rx-tx"; 340 }; 341 342 pata@10200 { 343 compatible = "fsl,mpc5121-pata"; 344 reg = <0x10200 0x100>; 345 interrupts = <5 0x8>; 346 clocks = <&clks MPC512x_CLK_PATA>; 347 clock-names = "ipg"; 348 }; 349 350 /* 512x PSCs are not 52xx PSC compatible */ 351 352 /* PSC0 */ 353 psc@11000 { 354 compatible = "fsl,mpc5121-psc"; 355 reg = <0x11000 0x100>; 356 interrupts = <40 0x8>; 357 fsl,rx-fifo-size = <16>; 358 fsl,tx-fifo-size = <16>; 359 clocks = <&clks MPC512x_CLK_PSC0>, 360 <&clks MPC512x_CLK_PSC0_MCLK>; 361 clock-names = "ipg", "mclk"; 362 }; 363 364 /* PSC1 */ 365 psc@11100 { 366 compatible = "fsl,mpc5121-psc"; 367 reg = <0x11100 0x100>; 368 interrupts = <40 0x8>; 369 fsl,rx-fifo-size = <16>; 370 fsl,tx-fifo-size = <16>; 371 clocks = <&clks MPC512x_CLK_PSC1>, 372 <&clks MPC512x_CLK_PSC1_MCLK>; 373 clock-names = "ipg", "mclk"; 374 }; 375 376 /* PSC2 */ 377 psc@11200 { 378 compatible = "fsl,mpc5121-psc"; 379 reg = <0x11200 0x100>; 380 interrupts = <40 0x8>; 381 fsl,rx-fifo-size = <16>; 382 fsl,tx-fifo-size = <16>; 383 clocks = <&clks MPC512x_CLK_PSC2>, 384 <&clks MPC512x_CLK_PSC2_MCLK>; 385 clock-names = "ipg", "mclk"; 386 }; 387 388 /* PSC3 */ 389 psc@11300 { 390 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 391 reg = <0x11300 0x100>; 392 interrupts = <40 0x8>; 393 fsl,rx-fifo-size = <16>; 394 fsl,tx-fifo-size = <16>; 395 clocks = <&clks MPC512x_CLK_PSC3>, 396 <&clks MPC512x_CLK_PSC3_MCLK>; 397 clock-names = "ipg", "mclk"; 398 }; 399 400 /* PSC4 */ 401 psc@11400 { 402 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 403 reg = <0x11400 0x100>; 404 interrupts = <40 0x8>; 405 fsl,rx-fifo-size = <16>; 406 fsl,tx-fifo-size = <16>; 407 clocks = <&clks MPC512x_CLK_PSC4>, 408 <&clks MPC512x_CLK_PSC4_MCLK>; 409 clock-names = "ipg", "mclk"; 410 }; 411 412 /* PSC5 */ 413 psc@11500 { 414 compatible = "fsl,mpc5121-psc"; 415 reg = <0x11500 0x100>; 416 interrupts = <40 0x8>; 417 fsl,rx-fifo-size = <16>; 418 fsl,tx-fifo-size = <16>; 419 clocks = <&clks MPC512x_CLK_PSC5>, 420 <&clks MPC512x_CLK_PSC5_MCLK>; 421 clock-names = "ipg", "mclk"; 422 }; 423 424 /* PSC6 */ 425 psc@11600 { 426 compatible = "fsl,mpc5121-psc"; 427 reg = <0x11600 0x100>; 428 interrupts = <40 0x8>; 429 fsl,rx-fifo-size = <16>; 430 fsl,tx-fifo-size = <16>; 431 clocks = <&clks MPC512x_CLK_PSC6>, 432 <&clks MPC512x_CLK_PSC6_MCLK>; 433 clock-names = "ipg", "mclk"; 434 }; 435 436 /* PSC7 */ 437 psc@11700 { 438 compatible = "fsl,mpc5121-psc"; 439 reg = <0x11700 0x100>; 440 interrupts = <40 0x8>; 441 fsl,rx-fifo-size = <16>; 442 fsl,tx-fifo-size = <16>; 443 clocks = <&clks MPC512x_CLK_PSC7>, 444 <&clks MPC512x_CLK_PSC7_MCLK>; 445 clock-names = "ipg", "mclk"; 446 }; 447 448 /* PSC8 */ 449 psc@11800 { 450 compatible = "fsl,mpc5121-psc"; 451 reg = <0x11800 0x100>; 452 interrupts = <40 0x8>; 453 fsl,rx-fifo-size = <16>; 454 fsl,tx-fifo-size = <16>; 455 clocks = <&clks MPC512x_CLK_PSC8>, 456 <&clks MPC512x_CLK_PSC8_MCLK>; 457 clock-names = "ipg", "mclk"; 458 }; 459 460 /* PSC9 */ 461 psc@11900 { 462 compatible = "fsl,mpc5121-psc"; 463 reg = <0x11900 0x100>; 464 interrupts = <40 0x8>; 465 fsl,rx-fifo-size = <16>; 466 fsl,tx-fifo-size = <16>; 467 clocks = <&clks MPC512x_CLK_PSC9>, 468 <&clks MPC512x_CLK_PSC9_MCLK>; 469 clock-names = "ipg", "mclk"; 470 }; 471 472 /* PSC10 */ 473 psc@11a00 { 474 compatible = "fsl,mpc5121-psc"; 475 reg = <0x11a00 0x100>; 476 interrupts = <40 0x8>; 477 fsl,rx-fifo-size = <16>; 478 fsl,tx-fifo-size = <16>; 479 clocks = <&clks MPC512x_CLK_PSC10>, 480 <&clks MPC512x_CLK_PSC10_MCLK>; 481 clock-names = "ipg", "mclk"; 482 }; 483 484 /* PSC11 */ 485 psc@11b00 { 486 compatible = "fsl,mpc5121-psc"; 487 reg = <0x11b00 0x100>; 488 interrupts = <40 0x8>; 489 fsl,rx-fifo-size = <16>; 490 fsl,tx-fifo-size = <16>; 491 clocks = <&clks MPC512x_CLK_PSC11>, 492 <&clks MPC512x_CLK_PSC11_MCLK>; 493 clock-names = "ipg", "mclk"; 494 }; 495 496 pscfifo@11f00 { 497 compatible = "fsl,mpc5121-psc-fifo"; 498 reg = <0x11f00 0x100>; 499 interrupts = <40 0x8>; 500 clocks = <&clks MPC512x_CLK_PSC_FIFO>; 501 clock-names = "ipg"; 502 }; 503 504 dma0: dma@14000 { 505 compatible = "fsl,mpc5121-dma"; 506 reg = <0x14000 0x1800>; 507 interrupts = <65 0x8>; 508 #dma-cells = <1>; 509 }; 510 }; 511 512 pci: pci@80008500 { 513 compatible = "fsl,mpc5121-pci"; 514 device_type = "pci"; 515 interrupts = <1 0x8>; 516 clock-frequency = <0>; 517 #address-cells = <3>; 518 #size-cells = <2>; 519 #interrupt-cells = <1>; 520 clocks = <&clks MPC512x_CLK_PCI>; 521 clock-names = "ipg"; 522 523 reg = <0x80008500 0x100 /* internal registers */ 524 0x80008300 0x8>; /* config space access registers */ 525 bus-range = <0x0 0x0>; 526 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 527 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 528 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>; 529 }; 530}; 531