1/* 2 * base MPC5121 Device Tree Source 3 * 4 * Copyright 2007-2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "mpc5121"; 16 compatible = "fsl,mpc5121"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 interrupt-parent = <&ipic>; 20 21 aliases { 22 ethernet0 = ð0; 23 pci = &pci; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 PowerPC,5121@0 { 31 device_type = "cpu"; 32 reg = <0>; 33 d-cache-line-size = <0x20>; /* 32 bytes */ 34 i-cache-line-size = <0x20>; /* 32 bytes */ 35 d-cache-size = <0x8000>; /* L1, 32K */ 36 i-cache-size = <0x8000>; /* L1, 32K */ 37 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */ 38 bus-frequency = <198000000>; /* 198 MHz csb bus */ 39 clock-frequency = <396000000>; /* 396 MHz ppc core */ 40 }; 41 }; 42 43 memory { 44 device_type = "memory"; 45 reg = <0x00000000 0x10000000>; /* 256MB at 0 */ 46 }; 47 48 mbx@20000000 { 49 compatible = "fsl,mpc5121-mbx"; 50 reg = <0x20000000 0x4000>; 51 interrupts = <66 0x8>; 52 }; 53 54 sram@30000000 { 55 compatible = "fsl,mpc5121-sram"; 56 reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */ 57 }; 58 59 nfc@40000000 { 60 compatible = "fsl,mpc5121-nfc"; 61 reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */ 62 interrupts = <6 8>; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 }; 66 67 localbus@80000020 { 68 compatible = "fsl,mpc5121-localbus"; 69 #address-cells = <2>; 70 #size-cells = <1>; 71 reg = <0x80000020 0x40>; 72 interrupts = <7 0x8>; 73 ranges = <0x0 0x0 0xfc000000 0x04000000>; 74 }; 75 76 soc@80000000 { 77 compatible = "fsl,mpc5121-immr"; 78 #address-cells = <1>; 79 #size-cells = <1>; 80 ranges = <0x0 0x80000000 0x400000>; 81 reg = <0x80000000 0x400000>; 82 bus-frequency = <66000000>; /* 66 MHz ips bus */ 83 84 85 /* 86 * IPIC 87 * interrupts cell = <intr #, sense> 88 * sense values match linux IORESOURCE_IRQ_* defines: 89 * sense == 8: Level, low assertion 90 * sense == 2: Edge, high-to-low change 91 */ 92 ipic: interrupt-controller@c00 { 93 compatible = "fsl,mpc5121-ipic", "fsl,ipic"; 94 interrupt-controller; 95 #address-cells = <0>; 96 #interrupt-cells = <2>; 97 reg = <0xc00 0x100>; 98 }; 99 100 /* Watchdog timer */ 101 wdt@900 { 102 compatible = "fsl,mpc5121-wdt"; 103 reg = <0x900 0x100>; 104 }; 105 106 /* Real time clock */ 107 rtc@a00 { 108 compatible = "fsl,mpc5121-rtc"; 109 reg = <0xa00 0x100>; 110 interrupts = <79 0x8 80 0x8>; 111 }; 112 113 /* Reset module */ 114 reset@e00 { 115 compatible = "fsl,mpc5121-reset"; 116 reg = <0xe00 0x100>; 117 }; 118 119 /* Clock control */ 120 clock@f00 { 121 compatible = "fsl,mpc5121-clock"; 122 reg = <0xf00 0x100>; 123 }; 124 125 /* Power Management Controller */ 126 pmc@1000{ 127 compatible = "fsl,mpc5121-pmc"; 128 reg = <0x1000 0x100>; 129 interrupts = <83 0x8>; 130 }; 131 132 gpio@1100 { 133 compatible = "fsl,mpc5121-gpio"; 134 reg = <0x1100 0x100>; 135 interrupts = <78 0x8>; 136 }; 137 138 can@1300 { 139 compatible = "fsl,mpc5121-mscan"; 140 reg = <0x1300 0x80>; 141 interrupts = <12 0x8>; 142 }; 143 144 can@1380 { 145 compatible = "fsl,mpc5121-mscan"; 146 reg = <0x1380 0x80>; 147 interrupts = <13 0x8>; 148 }; 149 150 sdhc@1500 { 151 compatible = "fsl,mpc5121-sdhc"; 152 reg = <0x1500 0x100>; 153 interrupts = <8 0x8>; 154 dmas = <&dma0 30>; 155 dma-names = "rx-tx"; 156 }; 157 158 i2c@1700 { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 162 reg = <0x1700 0x20>; 163 interrupts = <9 0x8>; 164 }; 165 166 i2c@1720 { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 170 reg = <0x1720 0x20>; 171 interrupts = <10 0x8>; 172 }; 173 174 i2c@1740 { 175 #address-cells = <1>; 176 #size-cells = <0>; 177 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 178 reg = <0x1740 0x20>; 179 interrupts = <11 0x8>; 180 }; 181 182 i2ccontrol@1760 { 183 compatible = "fsl,mpc5121-i2c-ctrl"; 184 reg = <0x1760 0x8>; 185 }; 186 187 axe@2000 { 188 compatible = "fsl,mpc5121-axe"; 189 reg = <0x2000 0x100>; 190 interrupts = <42 0x8>; 191 }; 192 193 display@2100 { 194 compatible = "fsl,mpc5121-diu"; 195 reg = <0x2100 0x100>; 196 interrupts = <64 0x8>; 197 }; 198 199 can@2300 { 200 compatible = "fsl,mpc5121-mscan"; 201 reg = <0x2300 0x80>; 202 interrupts = <90 0x8>; 203 }; 204 205 can@2380 { 206 compatible = "fsl,mpc5121-mscan"; 207 reg = <0x2380 0x80>; 208 interrupts = <91 0x8>; 209 }; 210 211 viu@2400 { 212 compatible = "fsl,mpc5121-viu"; 213 reg = <0x2400 0x400>; 214 interrupts = <67 0x8>; 215 }; 216 217 mdio@2800 { 218 compatible = "fsl,mpc5121-fec-mdio"; 219 reg = <0x2800 0x800>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 }; 223 224 eth0: ethernet@2800 { 225 device_type = "network"; 226 compatible = "fsl,mpc5121-fec"; 227 reg = <0x2800 0x800>; 228 local-mac-address = [ 00 00 00 00 00 00 ]; 229 interrupts = <4 0x8>; 230 }; 231 232 /* USB1 using external ULPI PHY */ 233 usb@3000 { 234 compatible = "fsl,mpc5121-usb2-dr"; 235 reg = <0x3000 0x600>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 interrupts = <43 0x8>; 239 dr_mode = "otg"; 240 phy_type = "ulpi"; 241 }; 242 243 /* USB0 using internal UTMI PHY */ 244 usb@4000 { 245 compatible = "fsl,mpc5121-usb2-dr"; 246 reg = <0x4000 0x600>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 interrupts = <44 0x8>; 250 dr_mode = "otg"; 251 phy_type = "utmi_wide"; 252 }; 253 254 /* IO control */ 255 ioctl@a000 { 256 compatible = "fsl,mpc5121-ioctl"; 257 reg = <0xA000 0x1000>; 258 }; 259 260 /* LocalPlus controller */ 261 lpc@10000 { 262 compatible = "fsl,mpc5121-lpc"; 263 reg = <0x10000 0x200>; 264 }; 265 266 pata@10200 { 267 compatible = "fsl,mpc5121-pata"; 268 reg = <0x10200 0x100>; 269 interrupts = <5 0x8>; 270 }; 271 272 /* 512x PSCs are not 52xx PSC compatible */ 273 274 /* PSC0 */ 275 psc@11000 { 276 compatible = "fsl,mpc5121-psc"; 277 reg = <0x11000 0x100>; 278 interrupts = <40 0x8>; 279 fsl,rx-fifo-size = <16>; 280 fsl,tx-fifo-size = <16>; 281 }; 282 283 /* PSC1 */ 284 psc@11100 { 285 compatible = "fsl,mpc5121-psc"; 286 reg = <0x11100 0x100>; 287 interrupts = <40 0x8>; 288 fsl,rx-fifo-size = <16>; 289 fsl,tx-fifo-size = <16>; 290 }; 291 292 /* PSC2 */ 293 psc@11200 { 294 compatible = "fsl,mpc5121-psc"; 295 reg = <0x11200 0x100>; 296 interrupts = <40 0x8>; 297 fsl,rx-fifo-size = <16>; 298 fsl,tx-fifo-size = <16>; 299 }; 300 301 /* PSC3 */ 302 psc@11300 { 303 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 304 reg = <0x11300 0x100>; 305 interrupts = <40 0x8>; 306 fsl,rx-fifo-size = <16>; 307 fsl,tx-fifo-size = <16>; 308 }; 309 310 /* PSC4 */ 311 psc@11400 { 312 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 313 reg = <0x11400 0x100>; 314 interrupts = <40 0x8>; 315 fsl,rx-fifo-size = <16>; 316 fsl,tx-fifo-size = <16>; 317 }; 318 319 /* PSC5 */ 320 psc@11500 { 321 compatible = "fsl,mpc5121-psc"; 322 reg = <0x11500 0x100>; 323 interrupts = <40 0x8>; 324 fsl,rx-fifo-size = <16>; 325 fsl,tx-fifo-size = <16>; 326 }; 327 328 /* PSC6 */ 329 psc@11600 { 330 compatible = "fsl,mpc5121-psc"; 331 reg = <0x11600 0x100>; 332 interrupts = <40 0x8>; 333 fsl,rx-fifo-size = <16>; 334 fsl,tx-fifo-size = <16>; 335 }; 336 337 /* PSC7 */ 338 psc@11700 { 339 compatible = "fsl,mpc5121-psc"; 340 reg = <0x11700 0x100>; 341 interrupts = <40 0x8>; 342 fsl,rx-fifo-size = <16>; 343 fsl,tx-fifo-size = <16>; 344 }; 345 346 /* PSC8 */ 347 psc@11800 { 348 compatible = "fsl,mpc5121-psc"; 349 reg = <0x11800 0x100>; 350 interrupts = <40 0x8>; 351 fsl,rx-fifo-size = <16>; 352 fsl,tx-fifo-size = <16>; 353 }; 354 355 /* PSC9 */ 356 psc@11900 { 357 compatible = "fsl,mpc5121-psc"; 358 reg = <0x11900 0x100>; 359 interrupts = <40 0x8>; 360 fsl,rx-fifo-size = <16>; 361 fsl,tx-fifo-size = <16>; 362 }; 363 364 /* PSC10 */ 365 psc@11a00 { 366 compatible = "fsl,mpc5121-psc"; 367 reg = <0x11a00 0x100>; 368 interrupts = <40 0x8>; 369 fsl,rx-fifo-size = <16>; 370 fsl,tx-fifo-size = <16>; 371 }; 372 373 /* PSC11 */ 374 psc@11b00 { 375 compatible = "fsl,mpc5121-psc"; 376 reg = <0x11b00 0x100>; 377 interrupts = <40 0x8>; 378 fsl,rx-fifo-size = <16>; 379 fsl,tx-fifo-size = <16>; 380 }; 381 382 pscfifo@11f00 { 383 compatible = "fsl,mpc5121-psc-fifo"; 384 reg = <0x11f00 0x100>; 385 interrupts = <40 0x8>; 386 }; 387 388 dma0: dma@14000 { 389 compatible = "fsl,mpc5121-dma"; 390 reg = <0x14000 0x1800>; 391 interrupts = <65 0x8>; 392 }; 393 }; 394 395 pci: pci@80008500 { 396 compatible = "fsl,mpc5121-pci"; 397 device_type = "pci"; 398 interrupts = <1 0x8>; 399 clock-frequency = <0>; 400 #address-cells = <3>; 401 #size-cells = <2>; 402 #interrupt-cells = <1>; 403 404 reg = <0x80008500 0x100 /* internal registers */ 405 0x80008300 0x8>; /* config space access registers */ 406 bus-range = <0x0 0x0>; 407 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 408 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 409 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>; 410 }; 411}; 412