1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * base MPC5121 Device Tree Source 4 * 5 * Copyright 2007-2008 Freescale Semiconductor Inc. 6 */ 7 8#include <dt-bindings/clock/mpc512x-clock.h> 9 10/dts-v1/; 11 12/ { 13 model = "mpc5121"; 14 compatible = "fsl,mpc5121"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 interrupt-parent = <&ipic>; 18 19 aliases { 20 ethernet0 = ð0; 21 pci = &pci; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 PowerPC,5121@0 { 29 device_type = "cpu"; 30 reg = <0>; 31 d-cache-line-size = <0x20>; /* 32 bytes */ 32 i-cache-line-size = <0x20>; /* 32 bytes */ 33 d-cache-size = <0x8000>; /* L1, 32K */ 34 i-cache-size = <0x8000>; /* L1, 32K */ 35 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */ 36 bus-frequency = <198000000>; /* 198 MHz csb bus */ 37 clock-frequency = <396000000>; /* 396 MHz ppc core */ 38 }; 39 }; 40 41 memory { 42 device_type = "memory"; 43 reg = <0x00000000 0x10000000>; /* 256MB at 0 */ 44 }; 45 46 mbx@20000000 { 47 compatible = "fsl,mpc5121-mbx"; 48 reg = <0x20000000 0x4000>; 49 interrupts = <66 0x8>; 50 clocks = <&clks MPC512x_CLK_MBX_BUS>, 51 <&clks MPC512x_CLK_MBX_3D>, 52 <&clks MPC512x_CLK_MBX>; 53 clock-names = "mbx-bus", "mbx-3d", "mbx"; 54 }; 55 56 sram@30000000 { 57 compatible = "fsl,mpc5121-sram"; 58 reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */ 59 }; 60 61 nfc@40000000 { 62 compatible = "fsl,mpc5121-nfc"; 63 reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */ 64 interrupts = <6 8>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 clocks = <&clks MPC512x_CLK_NFC>; 68 clock-names = "ipg"; 69 }; 70 71 localbus@80000020 { 72 compatible = "fsl,mpc5121-localbus"; 73 #address-cells = <2>; 74 #size-cells = <1>; 75 reg = <0x80000020 0x40>; 76 ranges = <0x0 0x0 0xfc000000 0x04000000>; 77 }; 78 79 clocks { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 osc: osc { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <33000000>; 87 }; 88 }; 89 90 soc@80000000 { 91 compatible = "fsl,mpc5121-immr"; 92 #address-cells = <1>; 93 #size-cells = <1>; 94 ranges = <0x0 0x80000000 0x400000>; 95 reg = <0x80000000 0x400000>; 96 bus-frequency = <66000000>; /* 66 MHz ips bus */ 97 98 99 /* 100 * IPIC 101 * interrupts cell = <intr #, sense> 102 * sense values match linux IORESOURCE_IRQ_* defines: 103 * sense == 8: Level, low assertion 104 * sense == 2: Edge, high-to-low change 105 */ 106 ipic: interrupt-controller@c00 { 107 compatible = "fsl,mpc5121-ipic", "fsl,ipic"; 108 interrupt-controller; 109 #address-cells = <0>; 110 #interrupt-cells = <2>; 111 reg = <0xc00 0x100>; 112 }; 113 114 /* Watchdog timer */ 115 wdt@900 { 116 compatible = "fsl,mpc5121-wdt"; 117 reg = <0x900 0x100>; 118 }; 119 120 /* Real time clock */ 121 rtc@a00 { 122 compatible = "fsl,mpc5121-rtc"; 123 reg = <0xa00 0x100>; 124 interrupts = <79 0x8 80 0x8>; 125 }; 126 127 /* Reset module */ 128 reset@e00 { 129 compatible = "fsl,mpc5121-reset"; 130 reg = <0xe00 0x100>; 131 }; 132 133 /* Clock control */ 134 clks: clock@f00 { 135 compatible = "fsl,mpc5121-clock"; 136 reg = <0xf00 0x100>; 137 #clock-cells = <1>; 138 clocks = <&osc>; 139 clock-names = "osc"; 140 }; 141 142 /* Power Management Controller */ 143 pmc@1000 { 144 compatible = "fsl,mpc5121-pmc"; 145 reg = <0x1000 0x100>; 146 interrupts = <83 0x8>; 147 }; 148 149 gpio@1100 { 150 compatible = "fsl,mpc5121-gpio"; 151 reg = <0x1100 0x100>; 152 interrupts = <78 0x8>; 153 }; 154 155 can@1300 { 156 compatible = "fsl,mpc5121-mscan"; 157 reg = <0x1300 0x80>; 158 interrupts = <12 0x8>; 159 clocks = <&clks MPC512x_CLK_BDLC>, 160 <&clks MPC512x_CLK_IPS>, 161 <&clks MPC512x_CLK_SYS>, 162 <&clks MPC512x_CLK_REF>, 163 <&clks MPC512x_CLK_MSCAN0_MCLK>; 164 clock-names = "ipg", "ips", "sys", "ref", "mclk"; 165 }; 166 167 can@1380 { 168 compatible = "fsl,mpc5121-mscan"; 169 reg = <0x1380 0x80>; 170 interrupts = <13 0x8>; 171 clocks = <&clks MPC512x_CLK_BDLC>, 172 <&clks MPC512x_CLK_IPS>, 173 <&clks MPC512x_CLK_SYS>, 174 <&clks MPC512x_CLK_REF>, 175 <&clks MPC512x_CLK_MSCAN1_MCLK>; 176 clock-names = "ipg", "ips", "sys", "ref", "mclk"; 177 }; 178 179 sdhc@1500 { 180 compatible = "fsl,mpc5121-sdhc"; 181 reg = <0x1500 0x100>; 182 interrupts = <8 0x8>; 183 dmas = <&dma0 30>; 184 dma-names = "rx-tx"; 185 clocks = <&clks MPC512x_CLK_IPS>, 186 <&clks MPC512x_CLK_SDHC>; 187 clock-names = "ipg", "per"; 188 }; 189 190 i2c@1700 { 191 #address-cells = <1>; 192 #size-cells = <0>; 193 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 194 reg = <0x1700 0x20>; 195 interrupts = <9 0x8>; 196 clocks = <&clks MPC512x_CLK_I2C>; 197 clock-names = "ipg"; 198 }; 199 200 i2c@1720 { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 204 reg = <0x1720 0x20>; 205 interrupts = <10 0x8>; 206 clocks = <&clks MPC512x_CLK_I2C>; 207 clock-names = "ipg"; 208 }; 209 210 i2c@1740 { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 214 reg = <0x1740 0x20>; 215 interrupts = <11 0x8>; 216 clocks = <&clks MPC512x_CLK_I2C>; 217 clock-names = "ipg"; 218 }; 219 220 i2ccontrol@1760 { 221 compatible = "fsl,mpc5121-i2c-ctrl"; 222 reg = <0x1760 0x8>; 223 }; 224 225 axe@2000 { 226 compatible = "fsl,mpc5121-axe"; 227 reg = <0x2000 0x100>; 228 interrupts = <42 0x8>; 229 clocks = <&clks MPC512x_CLK_AXE>; 230 clock-names = "ipg"; 231 }; 232 233 display@2100 { 234 compatible = "fsl,mpc5121-diu"; 235 reg = <0x2100 0x100>; 236 interrupts = <64 0x8>; 237 clocks = <&clks MPC512x_CLK_DIU>; 238 clock-names = "ipg"; 239 }; 240 241 can@2300 { 242 compatible = "fsl,mpc5121-mscan"; 243 reg = <0x2300 0x80>; 244 interrupts = <90 0x8>; 245 clocks = <&clks MPC512x_CLK_BDLC>, 246 <&clks MPC512x_CLK_IPS>, 247 <&clks MPC512x_CLK_SYS>, 248 <&clks MPC512x_CLK_REF>, 249 <&clks MPC512x_CLK_MSCAN2_MCLK>; 250 clock-names = "ipg", "ips", "sys", "ref", "mclk"; 251 }; 252 253 can@2380 { 254 compatible = "fsl,mpc5121-mscan"; 255 reg = <0x2380 0x80>; 256 interrupts = <91 0x8>; 257 clocks = <&clks MPC512x_CLK_BDLC>, 258 <&clks MPC512x_CLK_IPS>, 259 <&clks MPC512x_CLK_SYS>, 260 <&clks MPC512x_CLK_REF>, 261 <&clks MPC512x_CLK_MSCAN3_MCLK>; 262 clock-names = "ipg", "ips", "sys", "ref", "mclk"; 263 }; 264 265 viu@2400 { 266 compatible = "fsl,mpc5121-viu"; 267 reg = <0x2400 0x400>; 268 interrupts = <67 0x8>; 269 clocks = <&clks MPC512x_CLK_VIU>; 270 clock-names = "ipg"; 271 }; 272 273 mdio@2800 { 274 compatible = "fsl,mpc5121-fec-mdio"; 275 reg = <0x2800 0x800>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 clocks = <&clks MPC512x_CLK_FEC>; 279 clock-names = "per"; 280 }; 281 282 eth0: ethernet@2800 { 283 device_type = "network"; 284 compatible = "fsl,mpc5121-fec"; 285 reg = <0x2800 0x800>; 286 local-mac-address = [ 00 00 00 00 00 00 ]; 287 interrupts = <4 0x8>; 288 clocks = <&clks MPC512x_CLK_FEC>; 289 clock-names = "per"; 290 }; 291 292 /* USB1 using external ULPI PHY */ 293 usb@3000 { 294 compatible = "fsl,mpc5121-usb2-dr"; 295 reg = <0x3000 0x600>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 interrupts = <43 0x8>; 299 dr_mode = "otg"; 300 phy_type = "ulpi"; 301 clocks = <&clks MPC512x_CLK_USB1>; 302 clock-names = "ipg"; 303 }; 304 305 /* USB0 using internal UTMI PHY */ 306 usb@4000 { 307 compatible = "fsl,mpc5121-usb2-dr"; 308 reg = <0x4000 0x600>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 interrupts = <44 0x8>; 312 dr_mode = "otg"; 313 phy_type = "utmi_wide"; 314 clocks = <&clks MPC512x_CLK_USB2>; 315 clock-names = "ipg"; 316 }; 317 318 /* IO control */ 319 ioctl@a000 { 320 compatible = "fsl,mpc5121-ioctl"; 321 reg = <0xA000 0x1000>; 322 }; 323 324 /* LocalPlus controller */ 325 lpc@10000 { 326 compatible = "fsl,mpc5121-lpc"; 327 reg = <0x10000 0x100>; 328 }; 329 330 sclpc@10100 { 331 compatible = "fsl,mpc512x-lpbfifo"; 332 reg = <0x10100 0x50>; 333 interrupts = <7 0x8>; 334 dmas = <&dma0 26>; 335 dma-names = "rx-tx"; 336 }; 337 338 pata@10200 { 339 compatible = "fsl,mpc5121-pata"; 340 reg = <0x10200 0x100>; 341 interrupts = <5 0x8>; 342 clocks = <&clks MPC512x_CLK_PATA>; 343 clock-names = "ipg"; 344 }; 345 346 /* 512x PSCs are not 52xx PSC compatible */ 347 348 /* PSC0 */ 349 psc@11000 { 350 compatible = "fsl,mpc5121-psc"; 351 reg = <0x11000 0x100>; 352 interrupts = <40 0x8>; 353 fsl,rx-fifo-size = <16>; 354 fsl,tx-fifo-size = <16>; 355 clocks = <&clks MPC512x_CLK_PSC0>, 356 <&clks MPC512x_CLK_PSC0_MCLK>; 357 clock-names = "ipg", "mclk"; 358 }; 359 360 /* PSC1 */ 361 psc@11100 { 362 compatible = "fsl,mpc5121-psc"; 363 reg = <0x11100 0x100>; 364 interrupts = <40 0x8>; 365 fsl,rx-fifo-size = <16>; 366 fsl,tx-fifo-size = <16>; 367 clocks = <&clks MPC512x_CLK_PSC1>, 368 <&clks MPC512x_CLK_PSC1_MCLK>; 369 clock-names = "ipg", "mclk"; 370 }; 371 372 /* PSC2 */ 373 psc@11200 { 374 compatible = "fsl,mpc5121-psc"; 375 reg = <0x11200 0x100>; 376 interrupts = <40 0x8>; 377 fsl,rx-fifo-size = <16>; 378 fsl,tx-fifo-size = <16>; 379 clocks = <&clks MPC512x_CLK_PSC2>, 380 <&clks MPC512x_CLK_PSC2_MCLK>; 381 clock-names = "ipg", "mclk"; 382 }; 383 384 /* PSC3 */ 385 psc@11300 { 386 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 387 reg = <0x11300 0x100>; 388 interrupts = <40 0x8>; 389 fsl,rx-fifo-size = <16>; 390 fsl,tx-fifo-size = <16>; 391 clocks = <&clks MPC512x_CLK_PSC3>, 392 <&clks MPC512x_CLK_PSC3_MCLK>; 393 clock-names = "ipg", "mclk"; 394 }; 395 396 /* PSC4 */ 397 psc@11400 { 398 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 399 reg = <0x11400 0x100>; 400 interrupts = <40 0x8>; 401 fsl,rx-fifo-size = <16>; 402 fsl,tx-fifo-size = <16>; 403 clocks = <&clks MPC512x_CLK_PSC4>, 404 <&clks MPC512x_CLK_PSC4_MCLK>; 405 clock-names = "ipg", "mclk"; 406 }; 407 408 /* PSC5 */ 409 psc@11500 { 410 compatible = "fsl,mpc5121-psc"; 411 reg = <0x11500 0x100>; 412 interrupts = <40 0x8>; 413 fsl,rx-fifo-size = <16>; 414 fsl,tx-fifo-size = <16>; 415 clocks = <&clks MPC512x_CLK_PSC5>, 416 <&clks MPC512x_CLK_PSC5_MCLK>; 417 clock-names = "ipg", "mclk"; 418 }; 419 420 /* PSC6 */ 421 psc@11600 { 422 compatible = "fsl,mpc5121-psc"; 423 reg = <0x11600 0x100>; 424 interrupts = <40 0x8>; 425 fsl,rx-fifo-size = <16>; 426 fsl,tx-fifo-size = <16>; 427 clocks = <&clks MPC512x_CLK_PSC6>, 428 <&clks MPC512x_CLK_PSC6_MCLK>; 429 clock-names = "ipg", "mclk"; 430 }; 431 432 /* PSC7 */ 433 psc@11700 { 434 compatible = "fsl,mpc5121-psc"; 435 reg = <0x11700 0x100>; 436 interrupts = <40 0x8>; 437 fsl,rx-fifo-size = <16>; 438 fsl,tx-fifo-size = <16>; 439 clocks = <&clks MPC512x_CLK_PSC7>, 440 <&clks MPC512x_CLK_PSC7_MCLK>; 441 clock-names = "ipg", "mclk"; 442 }; 443 444 /* PSC8 */ 445 psc@11800 { 446 compatible = "fsl,mpc5121-psc"; 447 reg = <0x11800 0x100>; 448 interrupts = <40 0x8>; 449 fsl,rx-fifo-size = <16>; 450 fsl,tx-fifo-size = <16>; 451 clocks = <&clks MPC512x_CLK_PSC8>, 452 <&clks MPC512x_CLK_PSC8_MCLK>; 453 clock-names = "ipg", "mclk"; 454 }; 455 456 /* PSC9 */ 457 psc@11900 { 458 compatible = "fsl,mpc5121-psc"; 459 reg = <0x11900 0x100>; 460 interrupts = <40 0x8>; 461 fsl,rx-fifo-size = <16>; 462 fsl,tx-fifo-size = <16>; 463 clocks = <&clks MPC512x_CLK_PSC9>, 464 <&clks MPC512x_CLK_PSC9_MCLK>; 465 clock-names = "ipg", "mclk"; 466 }; 467 468 /* PSC10 */ 469 psc@11a00 { 470 compatible = "fsl,mpc5121-psc"; 471 reg = <0x11a00 0x100>; 472 interrupts = <40 0x8>; 473 fsl,rx-fifo-size = <16>; 474 fsl,tx-fifo-size = <16>; 475 clocks = <&clks MPC512x_CLK_PSC10>, 476 <&clks MPC512x_CLK_PSC10_MCLK>; 477 clock-names = "ipg", "mclk"; 478 }; 479 480 /* PSC11 */ 481 psc@11b00 { 482 compatible = "fsl,mpc5121-psc"; 483 reg = <0x11b00 0x100>; 484 interrupts = <40 0x8>; 485 fsl,rx-fifo-size = <16>; 486 fsl,tx-fifo-size = <16>; 487 clocks = <&clks MPC512x_CLK_PSC11>, 488 <&clks MPC512x_CLK_PSC11_MCLK>; 489 clock-names = "ipg", "mclk"; 490 }; 491 492 pscfifo@11f00 { 493 compatible = "fsl,mpc5121-psc-fifo"; 494 reg = <0x11f00 0x100>; 495 interrupts = <40 0x8>; 496 clocks = <&clks MPC512x_CLK_PSC_FIFO>; 497 clock-names = "ipg"; 498 }; 499 500 dma0: dma@14000 { 501 compatible = "fsl,mpc5121-dma"; 502 reg = <0x14000 0x1800>; 503 interrupts = <65 0x8>; 504 #dma-cells = <1>; 505 }; 506 }; 507 508 pci: pci@80008500 { 509 compatible = "fsl,mpc5121-pci"; 510 device_type = "pci"; 511 interrupts = <1 0x8>; 512 clock-frequency = <0>; 513 #address-cells = <3>; 514 #size-cells = <2>; 515 #interrupt-cells = <1>; 516 clocks = <&clks MPC512x_CLK_PCI>; 517 clock-names = "ipg"; 518 519 reg = <0x80008500 0x100 /* internal registers */ 520 0x80008300 0x8>; /* config space access registers */ 521 bus-range = <0x0 0x0>; 522 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 523 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 524 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>; 525 }; 526}; 527