1/* 2 * Device Tree for the MGCOGE plattform from keymile 3 * 4 * Copyright 2008 DENX Software Engineering GmbH 5 * Heiko Schocher <hs@denx.de> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/dts-v1/; 14/ { 15 model = "MGCOGE"; 16 compatible = "keymile,mgcoge"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = ð0; 22 serial0 = &smc2; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 PowerPC,8247@0 { 30 device_type = "cpu"; 31 reg = <0>; 32 d-cache-line-size = <32>; 33 i-cache-line-size = <32>; 34 d-cache-size = <16384>; 35 i-cache-size = <16384>; 36 timebase-frequency = <0>; /* Filled in by U-Boot */ 37 clock-frequency = <0>; /* Filled in by U-Boot */ 38 bus-frequency = <0>; /* Filled in by U-Boot */ 39 }; 40 }; 41 42 localbus@f0010100 { 43 compatible = "fsl,mpc8247-localbus", 44 "fsl,pq2-localbus", 45 "simple-bus"; 46 #address-cells = <2>; 47 #size-cells = <1>; 48 reg = <0xf0010100 0x40>; 49 50 ranges = <0 0 0xfe000000 0x00400000 51 5 0 0x50000000 0x20000000 52 >; /* Filled in by U-Boot */ 53 54 flash@0,0 { 55 compatible = "cfi-flash"; 56 reg = <0 0x0 0x400000>; 57 #address-cells = <1>; 58 #size-cells = <1>; 59 bank-width = <1>; 60 device-width = <1>; 61 partition@0 { 62 label = "u-boot"; 63 reg = <0 0x40000>; 64 }; 65 partition@40000 { 66 label = "env"; 67 reg = <0x40000 0x20000>; 68 }; 69 partition@60000 { 70 label = "kernel"; 71 reg = <0x60000 0x220000>; 72 }; 73 partition@280000 { 74 label = "dtb"; 75 reg = <0x280000 0x20000>; 76 }; 77 }; 78 79 flash@5,0 { 80 compatible = "cfi-flash"; 81 reg = <5 0x0 0x2000000>; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 bank-width = <2>; 85 device-width = <2>; 86 partition@0 { 87 label = "ramdisk"; 88 reg = <0 0x7a0000>; 89 }; 90 partition@7a0000 { 91 label = "user"; 92 reg = <0x7a0000 0x1860000>; 93 }; 94 }; 95 }; 96 97 memory { 98 device_type = "memory"; 99 reg = <0 0>; /* Filled in by U-Boot */ 100 }; 101 102 soc@f0000000 { 103 #address-cells = <1>; 104 #size-cells = <1>; 105 compatible = "fsl,mpc8247-immr", "fsl,pq2-soc", "simple-bus"; 106 ranges = <0x00000000 0xf0000000 0x00053000>; 107 108 // Temporary until code stops depending on it. 109 device_type = "soc"; 110 111 cpm@119c0 { 112 #address-cells = <1>; 113 #size-cells = <1>; 114 #interrupt-cells = <2>; 115 compatible = "fsl,mpc8247-cpm", "fsl,cpm2", 116 "simple-bus"; 117 reg = <0x119c0 0x30>; 118 ranges; 119 120 muram { 121 compatible = "fsl,cpm-muram"; 122 #address-cells = <1>; 123 #size-cells = <1>; 124 ranges = <0 0 0x10000>; 125 126 data@0 { 127 compatible = "fsl,cpm-muram-data"; 128 reg = <0x80 0x1f80 0x9800 0x800>; 129 }; 130 }; 131 132 brg@119f0 { 133 compatible = "fsl,mpc8247-brg", 134 "fsl,cpm2-brg", 135 "fsl,cpm-brg"; 136 reg = <0x119f0 0x10 0x115f0 0x10>; 137 }; 138 139 /* Monitor port/SMC2 */ 140 smc2: serial@11a90 { 141 device_type = "serial"; 142 compatible = "fsl,mpc8247-smc-uart", 143 "fsl,cpm2-smc-uart"; 144 reg = <0x11a90 0x20 0x88fc 0x02>; 145 interrupts = <5 8>; 146 interrupt-parent = <&PIC>; 147 fsl,cpm-brg = <2>; 148 fsl,cpm-command = <0x21200000>; 149 current-speed = <0>; /* Filled in by U-Boot */ 150 }; 151 152 eth0: ethernet@11a60 { 153 device_type = "network"; 154 compatible = "fsl,mpc8247-scc-enet", 155 "fsl,cpm2-scc-enet"; 156 reg = <0x11a60 0x20 0x8300 0x100 0x11390 1>; 157 local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */ 158 interrupts = <43 8>; 159 interrupt-parent = <&PIC>; 160 linux,network-index = <0>; 161 fsl,cpm-command = <0xce00000>; 162 fixed-link = <0 0 10 0 0>; 163 }; 164 165 i2c@11860 { 166 compatible = "fsl,mpc8272-i2c", 167 "fsl,cpm2-i2c"; 168 reg = <0x11860 0x20 0x8afc 0x2>; 169 interrupts = <1 8>; 170 interrupt-parent = <&PIC>; 171 fsl,cpm-command = <0x29600000>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 }; 175 176 mdio@10d40 { 177 compatible = "fsl,cpm2-mdio-bitbang"; 178 reg = <0x10d00 0x14>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 fsl,mdio-pin = <12>; 182 fsl,mdc-pin = <13>; 183 184 phy0: ethernet-phy@0 { 185 reg = <0x0>; 186 }; 187 188 phy1: ethernet-phy@1 { 189 reg = <0x1>; 190 }; 191 }; 192 193 /* FCC1 management to switch */ 194 ethernet@11300 { 195 device_type = "network"; 196 compatible = "fsl,cpm2-fcc-enet"; 197 reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>; 198 local-mac-address = [ 00 01 02 03 04 07 ]; 199 interrupts = <32 8>; 200 interrupt-parent = <&PIC>; 201 phy-handle = <&phy0>; 202 linux,network-index = <1>; 203 fsl,cpm-command = <0x12000300>; 204 }; 205 206 /* FCC2 to redundant core unit over backplane */ 207 ethernet@11320 { 208 device_type = "network"; 209 compatible = "fsl,cpm2-fcc-enet"; 210 reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>; 211 local-mac-address = [ 00 01 02 03 04 08 ]; 212 interrupts = <33 8>; 213 interrupt-parent = <&PIC>; 214 phy-handle = <&phy1>; 215 linux,network-index = <2>; 216 fsl,cpm-command = <0x16200300>; 217 }; 218 }; 219 220 PIC: interrupt-controller@10c00 { 221 #interrupt-cells = <2>; 222 interrupt-controller; 223 reg = <0x10c00 0x80>; 224 compatible = "fsl,mpc8247-pic", "fsl,pq2-pic"; 225 }; 226 }; 227}; 228