1/*
2 * Freescale Media5200 board Device Tree Source
3 *
4 * Copyright 2009 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 * Steven Cavanagh <scavanagh@secretlab.ca>
7 *
8 * This program is free software; you can redistribute  it and/or modify it
9 * under  the terms of  the GNU General  Public License as published by the
10 * Free Software Foundation;  either version 2 of the  License, or (at your
11 * option) any later version.
12 */
13
14/include/ "mpc5200b.dtsi"
15
16/ {
17	model = "fsl,media5200";
18	compatible = "fsl,media5200";
19
20	aliases {
21		console = &console;
22		ethernet0 = &eth0;
23	};
24
25	chosen {
26		linux,stdout-path = &console;
27	};
28
29	cpus {
30		PowerPC,5200@0 {
31			timebase-frequency = <33000000>;	// 33 MHz, these were configured by U-Boot
32			bus-frequency = <132000000>;		// 132 MHz
33			clock-frequency = <396000000>;		// 396 MHz
34		};
35	};
36
37	memory {
38		reg = <0x00000000 0x08000000>;	// 128MB RAM
39	};
40
41	soc5200@f0000000 {
42		bus-frequency = <132000000>;// 132 MHz
43
44		timer@600 {	// General Purpose Timer
45			fsl,has-wdt;
46		};
47
48		psc@2000 {	// PSC1
49			status = "disabled";
50		};
51
52		psc@2200 {	// PSC2
53			status = "disabled";
54		};
55
56		psc@2400 {	// PSC3
57			status = "disabled";
58		};
59
60		psc@2600 {	// PSC4
61			status = "disabled";
62		};
63
64		psc@2800 {	// PSC5
65			status = "disabled";
66		};
67
68		// PSC6 in uart mode
69		console: psc@2c00 {		// PSC6
70			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
71		};
72
73		ethernet@3000 {
74			phy-handle = <&phy0>;
75		};
76
77		mdio@3000 {
78			phy0: ethernet-phy@0 {
79				reg = <0>;
80			};
81		};
82
83		usb@1000 {
84			reg = <0x1000 0x100>;
85		};
86	};
87
88	pci@f0000d00 {
89		interrupt-map-mask = <0xf800 0 0 7>;
90		interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
91				 0xc000 0 0 2 &media5200_fpga 0 3
92				 0xc000 0 0 3 &media5200_fpga 0 4
93				 0xc000 0 0 4 &media5200_fpga 0 5
94
95				 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
96				 0xc800 0 0 2 &media5200_fpga 0 4
97				 0xc800 0 0 3 &media5200_fpga 0 5
98				 0xc800 0 0 4 &media5200_fpga 0 2
99
100				 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
101				 0xd000 0 0 2 &media5200_fpga 0 5
102
103				 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
104				>;
105		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
106			  0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
107			  0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
108		interrupt-parent = <&mpc5200_pic>;
109	};
110
111	localbus {
112		ranges = < 0 0 0xfc000000 0x02000000
113			   1 0 0xfe000000 0x02000000
114			   2 0 0xf0010000 0x00010000
115			   3 0 0xf0020000 0x00010000 >;
116		flash@0,0 {
117			compatible = "amd,am29lv28ml", "cfi-flash";
118			reg = <0 0x0 0x2000000>;                // 32 MB
119			bank-width = <4>;                       // Width in bytes of the flash bank
120			device-width = <2>;                     // Two devices on each bank
121		};
122
123		flash@1,0 {
124			compatible = "amd,am29lv28ml", "cfi-flash";
125			reg = <1 0 0x2000000>;                  // 32 MB
126			bank-width = <4>;                       // Width in bytes of the flash bank
127			device-width = <2>;                     // Two devices on each bank
128		};
129
130		media5200_fpga: fpga@2,0 {
131			compatible = "fsl,media5200-fpga";
132			interrupt-controller;
133			#interrupt-cells = <2>;	// 0:bank 1:id; no type field
134			reg = <2 0 0x10000>;
135
136			interrupt-parent = <&mpc5200_pic>;
137			interrupts = <0 0 3	// IRQ bank 0
138			              1 1 3>;	// IRQ bank 1
139		};
140
141		uart@3,0 {
142			compatible = "ti,tl16c752bpt";
143			reg = <3 0 0x10000>;
144			interrupt-parent = <&media5200_fpga>;
145			interrupts = <0 0  0 1>; // 2 irqs
146		};
147	};
148};
149