1/* 2 * Device Tree Source for AMCC Glacier (460GT) 3 * 4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de> 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without 8 * any warranty of any kind, whether express or implied. 9 */ 10 11/dts-v1/; 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <1>; 16 model = "amcc,glacier"; 17 compatible = "amcc,glacier"; 18 dcr-parent = <&{/cpus/cpu@0}>; 19 20 aliases { 21 ethernet0 = &EMAC0; 22 ethernet1 = &EMAC1; 23 ethernet2 = &EMAC2; 24 ethernet3 = &EMAC3; 25 serial0 = &UART0; 26 serial1 = &UART1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu@0 { 34 device_type = "cpu"; 35 model = "PowerPC,460GT"; 36 reg = <0x00000000>; 37 clock-frequency = <0>; /* Filled in by U-Boot */ 38 timebase-frequency = <0>; /* Filled in by U-Boot */ 39 i-cache-line-size = <32>; 40 d-cache-line-size = <32>; 41 i-cache-size = <32768>; 42 d-cache-size = <32768>; 43 dcr-controller; 44 dcr-access-method = "native"; 45 next-level-cache = <&L2C0>; 46 }; 47 }; 48 49 memory { 50 device_type = "memory"; 51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 52 }; 53 54 UIC0: interrupt-controller0 { 55 compatible = "ibm,uic-460gt","ibm,uic"; 56 interrupt-controller; 57 cell-index = <0>; 58 dcr-reg = <0x0c0 0x009>; 59 #address-cells = <0>; 60 #size-cells = <0>; 61 #interrupt-cells = <2>; 62 }; 63 64 UIC1: interrupt-controller1 { 65 compatible = "ibm,uic-460gt","ibm,uic"; 66 interrupt-controller; 67 cell-index = <1>; 68 dcr-reg = <0x0d0 0x009>; 69 #address-cells = <0>; 70 #size-cells = <0>; 71 #interrupt-cells = <2>; 72 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 73 interrupt-parent = <&UIC0>; 74 }; 75 76 UIC2: interrupt-controller2 { 77 compatible = "ibm,uic-460gt","ibm,uic"; 78 interrupt-controller; 79 cell-index = <2>; 80 dcr-reg = <0x0e0 0x009>; 81 #address-cells = <0>; 82 #size-cells = <0>; 83 #interrupt-cells = <2>; 84 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 85 interrupt-parent = <&UIC0>; 86 }; 87 88 UIC3: interrupt-controller3 { 89 compatible = "ibm,uic-460gt","ibm,uic"; 90 interrupt-controller; 91 cell-index = <3>; 92 dcr-reg = <0x0f0 0x009>; 93 #address-cells = <0>; 94 #size-cells = <0>; 95 #interrupt-cells = <2>; 96 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 97 interrupt-parent = <&UIC0>; 98 }; 99 100 SDR0: sdr { 101 compatible = "ibm,sdr-460gt"; 102 dcr-reg = <0x00e 0x002>; 103 }; 104 105 CPR0: cpr { 106 compatible = "ibm,cpr-460gt"; 107 dcr-reg = <0x00c 0x002>; 108 }; 109 110 L2C0: l2c { 111 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; 112 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 113 0x030 0x008>; /* L2 cache DCR's */ 114 cache-line-size = <32>; /* 32 bytes */ 115 cache-size = <262144>; /* L2, 256K */ 116 interrupt-parent = <&UIC1>; 117 interrupts = <11 1>; 118 }; 119 120 plb { 121 compatible = "ibm,plb-460gt", "ibm,plb4"; 122 #address-cells = <2>; 123 #size-cells = <1>; 124 ranges; 125 clock-frequency = <0>; /* Filled in by U-Boot */ 126 127 SDRAM0: sdram { 128 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; 129 dcr-reg = <0x010 0x002>; 130 }; 131 132 CRYPTO: crypto@180000 { 133 compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto", 134 "amcc,ppc4xx-crypto"; 135 reg = <4 0x00180000 0x80400>; 136 interrupt-parent = <&UIC0>; 137 interrupts = <0x1d 0x4>; 138 }; 139 140 HWRNG: hwrng@110000 { 141 compatible = "amcc,ppc460ex-rng", "ppc4xx-rng"; 142 reg = <4 0x00110000 0x50>; 143 }; 144 145 MAL0: mcmal { 146 compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 147 dcr-reg = <0x180 0x062>; 148 num-tx-chans = <4>; 149 num-rx-chans = <32>; 150 #address-cells = <0>; 151 #size-cells = <0>; 152 interrupt-parent = <&UIC2>; 153 interrupts = < /*TXEOB*/ 0x6 0x4 154 /*RXEOB*/ 0x7 0x4 155 /*SERR*/ 0x3 0x4 156 /*TXDE*/ 0x4 0x4 157 /*RXDE*/ 0x5 0x4>; 158 desc-base-addr-high = <0x8>; 159 }; 160 161 POB0: opb { 162 compatible = "ibm,opb-460gt", "ibm,opb"; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 166 clock-frequency = <0>; /* Filled in by U-Boot */ 167 168 EBC0: ebc { 169 compatible = "ibm,ebc-460gt", "ibm,ebc"; 170 dcr-reg = <0x012 0x002>; 171 #address-cells = <2>; 172 #size-cells = <1>; 173 clock-frequency = <0>; /* Filled in by U-Boot */ 174 /* ranges property is supplied by U-Boot */ 175 interrupts = <0x6 0x4>; 176 interrupt-parent = <&UIC1>; 177 178 nor_flash@0,0 { 179 compatible = "amd,s29gl512n", "cfi-flash"; 180 bank-width = <2>; 181 reg = <0x00000000 0x00000000 0x04000000>; 182 #address-cells = <1>; 183 #size-cells = <1>; 184 partition@0 { 185 label = "kernel"; 186 reg = <0x00000000 0x001e0000>; 187 }; 188 partition@1e0000 { 189 label = "dtb"; 190 reg = <0x001e0000 0x00020000>; 191 }; 192 partition@200000 { 193 label = "ramdisk"; 194 reg = <0x00200000 0x01400000>; 195 }; 196 partition@1600000 { 197 label = "jffs2"; 198 reg = <0x01600000 0x00400000>; 199 }; 200 partition@1a00000 { 201 label = "user"; 202 reg = <0x01a00000 0x02560000>; 203 }; 204 partition@3f60000 { 205 label = "env"; 206 reg = <0x03f60000 0x00040000>; 207 }; 208 partition@3fa0000 { 209 label = "u-boot"; 210 reg = <0x03fa0000 0x00060000>; 211 }; 212 }; 213 214 ndfc@3,0 { 215 compatible = "ibm,ndfc"; 216 reg = <0x00000003 0x00000000 0x00002000>; 217 ccr = <0x00001000>; 218 bank-settings = <0x80002222>; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 222 nand { 223 #address-cells = <1>; 224 #size-cells = <1>; 225 226 partition@0 { 227 label = "u-boot"; 228 reg = <0x00000000 0x00100000>; 229 }; 230 partition@100000 { 231 label = "user"; 232 reg = <0x00000000 0x03f00000>; 233 }; 234 }; 235 }; 236 }; 237 238 UART0: serial@ef600300 { 239 device_type = "serial"; 240 compatible = "ns16550"; 241 reg = <0xef600300 0x00000008>; 242 virtual-reg = <0xef600300>; 243 clock-frequency = <0>; /* Filled in by U-Boot */ 244 current-speed = <0>; /* Filled in by U-Boot */ 245 interrupt-parent = <&UIC1>; 246 interrupts = <0x1 0x4>; 247 }; 248 249 UART1: serial@ef600400 { 250 device_type = "serial"; 251 compatible = "ns16550"; 252 reg = <0xef600400 0x00000008>; 253 virtual-reg = <0xef600400>; 254 clock-frequency = <0>; /* Filled in by U-Boot */ 255 current-speed = <0>; /* Filled in by U-Boot */ 256 interrupt-parent = <&UIC0>; 257 interrupts = <0x1 0x4>; 258 }; 259 260 UART2: serial@ef600500 { 261 device_type = "serial"; 262 compatible = "ns16550"; 263 reg = <0xef600500 0x00000008>; 264 virtual-reg = <0xef600500>; 265 clock-frequency = <0>; /* Filled in by U-Boot */ 266 current-speed = <0>; /* Filled in by U-Boot */ 267 interrupt-parent = <&UIC1>; 268 interrupts = <28 0x4>; 269 }; 270 271 UART3: serial@ef600600 { 272 device_type = "serial"; 273 compatible = "ns16550"; 274 reg = <0xef600600 0x00000008>; 275 virtual-reg = <0xef600600>; 276 clock-frequency = <0>; /* Filled in by U-Boot */ 277 current-speed = <0>; /* Filled in by U-Boot */ 278 interrupt-parent = <&UIC1>; 279 interrupts = <29 0x4>; 280 }; 281 282 IIC0: i2c@ef600700 { 283 compatible = "ibm,iic-460gt", "ibm,iic"; 284 reg = <0xef600700 0x00000014>; 285 interrupt-parent = <&UIC0>; 286 interrupts = <0x2 0x4>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 rtc@68 { 290 compatible = "st,m41t80"; 291 reg = <0x68>; 292 interrupt-parent = <&UIC2>; 293 interrupts = <0x19 0x8>; 294 }; 295 sttm@48 { 296 compatible = "ad,ad7414"; 297 reg = <0x48>; 298 interrupt-parent = <&UIC1>; 299 interrupts = <0x14 0x8>; 300 }; 301 }; 302 303 IIC1: i2c@ef600800 { 304 compatible = "ibm,iic-460gt", "ibm,iic"; 305 reg = <0xef600800 0x00000014>; 306 interrupt-parent = <&UIC0>; 307 interrupts = <0x3 0x4>; 308 }; 309 310 ZMII0: emac-zmii@ef600d00 { 311 compatible = "ibm,zmii-460gt", "ibm,zmii"; 312 reg = <0xef600d00 0x0000000c>; 313 }; 314 315 RGMII0: emac-rgmii@ef601500 { 316 compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 317 reg = <0xef601500 0x00000008>; 318 has-mdio; 319 }; 320 321 RGMII1: emac-rgmii@ef601600 { 322 compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 323 reg = <0xef601600 0x00000008>; 324 has-mdio; 325 }; 326 327 TAH0: emac-tah@ef601350 { 328 compatible = "ibm,tah-460gt", "ibm,tah"; 329 reg = <0xef601350 0x00000030>; 330 }; 331 332 TAH1: emac-tah@ef601450 { 333 compatible = "ibm,tah-460gt", "ibm,tah"; 334 reg = <0xef601450 0x00000030>; 335 }; 336 337 EMAC0: ethernet@ef600e00 { 338 device_type = "network"; 339 compatible = "ibm,emac-460gt", "ibm,emac4sync"; 340 interrupt-parent = <&EMAC0>; 341 interrupts = <0x0 0x1>; 342 #interrupt-cells = <1>; 343 #address-cells = <0>; 344 #size-cells = <0>; 345 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 346 /*Wake*/ 0x1 &UIC2 0x14 0x4>; 347 reg = <0xef600e00 0x000000c4>; 348 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 349 mal-device = <&MAL0>; 350 mal-tx-channel = <0>; 351 mal-rx-channel = <0>; 352 cell-index = <0>; 353 max-frame-size = <9000>; 354 rx-fifo-size = <4096>; 355 tx-fifo-size = <2048>; 356 rx-fifo-size-gige = <16384>; 357 phy-mode = "rgmii"; 358 phy-map = <0x00000000>; 359 rgmii-device = <&RGMII0>; 360 rgmii-channel = <0>; 361 tah-device = <&TAH0>; 362 tah-channel = <0>; 363 has-inverted-stacr-oc; 364 has-new-stacr-staopc; 365 }; 366 367 EMAC1: ethernet@ef600f00 { 368 device_type = "network"; 369 compatible = "ibm,emac-460gt", "ibm,emac4sync"; 370 interrupt-parent = <&EMAC1>; 371 interrupts = <0x0 0x1>; 372 #interrupt-cells = <1>; 373 #address-cells = <0>; 374 #size-cells = <0>; 375 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 376 /*Wake*/ 0x1 &UIC2 0x15 0x4>; 377 reg = <0xef600f00 0x000000c4>; 378 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 379 mal-device = <&MAL0>; 380 mal-tx-channel = <1>; 381 mal-rx-channel = <8>; 382 cell-index = <1>; 383 max-frame-size = <9000>; 384 rx-fifo-size = <4096>; 385 tx-fifo-size = <2048>; 386 rx-fifo-size-gige = <16384>; 387 phy-mode = "rgmii"; 388 phy-map = <0x00000000>; 389 rgmii-device = <&RGMII0>; 390 rgmii-channel = <1>; 391 tah-device = <&TAH1>; 392 tah-channel = <1>; 393 has-inverted-stacr-oc; 394 has-new-stacr-staopc; 395 mdio-device = <&EMAC0>; 396 }; 397 398 EMAC2: ethernet@ef601100 { 399 device_type = "network"; 400 compatible = "ibm,emac-460gt", "ibm,emac4sync"; 401 interrupt-parent = <&EMAC2>; 402 interrupts = <0x0 0x1>; 403 #interrupt-cells = <1>; 404 #address-cells = <0>; 405 #size-cells = <0>; 406 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 407 /*Wake*/ 0x1 &UIC2 0x16 0x4>; 408 reg = <0xef601100 0x000000c4>; 409 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 410 mal-device = <&MAL0>; 411 mal-tx-channel = <2>; 412 mal-rx-channel = <16>; 413 cell-index = <2>; 414 max-frame-size = <9000>; 415 rx-fifo-size = <4096>; 416 tx-fifo-size = <2048>; 417 rx-fifo-size-gige = <16384>; 418 tx-fifo-size-gige = <16384>; /* emac2&3 only */ 419 phy-mode = "rgmii"; 420 phy-map = <0x00000000>; 421 rgmii-device = <&RGMII1>; 422 rgmii-channel = <0>; 423 has-inverted-stacr-oc; 424 has-new-stacr-staopc; 425 mdio-device = <&EMAC0>; 426 }; 427 428 EMAC3: ethernet@ef601200 { 429 device_type = "network"; 430 compatible = "ibm,emac-460gt", "ibm,emac4sync"; 431 interrupt-parent = <&EMAC3>; 432 interrupts = <0x0 0x1>; 433 #interrupt-cells = <1>; 434 #address-cells = <0>; 435 #size-cells = <0>; 436 interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4 437 /*Wake*/ 0x1 &UIC2 0x17 0x4>; 438 reg = <0xef601200 0x000000c4>; 439 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 440 mal-device = <&MAL0>; 441 mal-tx-channel = <3>; 442 mal-rx-channel = <24>; 443 cell-index = <3>; 444 max-frame-size = <9000>; 445 rx-fifo-size = <4096>; 446 tx-fifo-size = <2048>; 447 rx-fifo-size-gige = <16384>; 448 tx-fifo-size-gige = <16384>; /* emac2&3 only */ 449 phy-mode = "rgmii"; 450 phy-map = <0x00000000>; 451 rgmii-device = <&RGMII1>; 452 rgmii-channel = <1>; 453 has-inverted-stacr-oc; 454 has-new-stacr-staopc; 455 mdio-device = <&EMAC0>; 456 }; 457 }; 458 459 PCIX0: pci@c0ec00000 { 460 device_type = "pci"; 461 #interrupt-cells = <1>; 462 #size-cells = <2>; 463 #address-cells = <3>; 464 compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix"; 465 primary; 466 large-inbound-windows; 467 enable-msi-hole; 468 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 469 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 470 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 471 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 472 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 473 474 /* Outbound ranges, one memory and one IO, 475 * later cannot be changed 476 */ 477 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 478 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 479 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 480 481 /* Inbound 2GB range starting at 0 */ 482 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 483 484 /* This drives busses 0 to 0x3f */ 485 bus-range = <0x0 0x3f>; 486 487 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 488 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 489 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; 490 }; 491 492 PCIE0: pciex@d00000000 { 493 device_type = "pci"; 494 #interrupt-cells = <1>; 495 #size-cells = <2>; 496 #address-cells = <3>; 497 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 498 primary; 499 port = <0x0>; /* port number */ 500 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 501 0x0000000c 0x08010000 0x00001000>; /* Registers */ 502 dcr-reg = <0x100 0x020>; 503 sdr-base = <0x300>; 504 505 /* Outbound ranges, one memory and one IO, 506 * later cannot be changed 507 */ 508 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 509 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 510 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 511 512 /* Inbound 2GB range starting at 0 */ 513 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 514 515 /* This drives busses 40 to 0x7f */ 516 bus-range = <0x40 0x7f>; 517 518 /* Legacy interrupts (note the weird polarity, the bridge seems 519 * to invert PCIe legacy interrupts). 520 * We are de-swizzling here because the numbers are actually for 521 * port of the root complex virtual P2P bridge. But I want 522 * to avoid putting a node for it in the tree, so the numbers 523 * below are basically de-swizzled numbers. 524 * The real slot is on idsel 0, so the swizzling is 1:1 525 */ 526 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 527 interrupt-map = < 528 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ 529 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ 530 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ 531 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; 532 }; 533 534 PCIE1: pciex@d20000000 { 535 device_type = "pci"; 536 #interrupt-cells = <1>; 537 #size-cells = <2>; 538 #address-cells = <3>; 539 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 540 primary; 541 port = <0x1>; /* port number */ 542 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 543 0x0000000c 0x08011000 0x00001000>; /* Registers */ 544 dcr-reg = <0x120 0x020>; 545 sdr-base = <0x340>; 546 547 /* Outbound ranges, one memory and one IO, 548 * later cannot be changed 549 */ 550 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 551 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 552 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 553 554 /* Inbound 2GB range starting at 0 */ 555 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 556 557 /* This drives busses 80 to 0xbf */ 558 bus-range = <0x80 0xbf>; 559 560 /* Legacy interrupts (note the weird polarity, the bridge seems 561 * to invert PCIe legacy interrupts). 562 * We are de-swizzling here because the numbers are actually for 563 * port of the root complex virtual P2P bridge. But I want 564 * to avoid putting a node for it in the tree, so the numbers 565 * below are basically de-swizzled numbers. 566 * The real slot is on idsel 0, so the swizzling is 1:1 567 */ 568 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 569 interrupt-map = < 570 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ 571 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ 572 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ 573 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; 574 }; 575 }; 576}; 577