1c06cf7daSStefan Roese/* 2c06cf7daSStefan Roese * Device Tree Source for AMCC Glacier (460GT) 3c06cf7daSStefan Roese * 4c06cf7daSStefan Roese * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 5c06cf7daSStefan Roese * 6c06cf7daSStefan Roese * This file is licensed under the terms of the GNU General Public 7c06cf7daSStefan Roese * License version 2. This program is licensed "as is" without 8c06cf7daSStefan Roese * any warranty of any kind, whether express or implied. 9c06cf7daSStefan Roese */ 10c06cf7daSStefan Roese 1171f34979SDavid Gibson/dts-v1/; 1271f34979SDavid Gibson 13c06cf7daSStefan Roese/ { 14c06cf7daSStefan Roese #address-cells = <2>; 15c06cf7daSStefan Roese #size-cells = <1>; 16c06cf7daSStefan Roese model = "amcc,glacier"; 17ded563cfSJosh Boyer compatible = "amcc,glacier"; 1871f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 19c06cf7daSStefan Roese 20c06cf7daSStefan Roese aliases { 21c06cf7daSStefan Roese ethernet0 = &EMAC0; 22c06cf7daSStefan Roese ethernet1 = &EMAC1; 23c06cf7daSStefan Roese ethernet2 = &EMAC2; 24c06cf7daSStefan Roese ethernet3 = &EMAC3; 25c06cf7daSStefan Roese serial0 = &UART0; 26c06cf7daSStefan Roese serial1 = &UART1; 27c06cf7daSStefan Roese }; 28c06cf7daSStefan Roese 29c06cf7daSStefan Roese cpus { 30c06cf7daSStefan Roese #address-cells = <1>; 31c06cf7daSStefan Roese #size-cells = <0>; 32c06cf7daSStefan Roese 33c06cf7daSStefan Roese cpu@0 { 34c06cf7daSStefan Roese device_type = "cpu"; 35c06cf7daSStefan Roese model = "PowerPC,460GT"; 3671f34979SDavid Gibson reg = <0x00000000>; 37c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 38c06cf7daSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3971f34979SDavid Gibson i-cache-line-size = <32>; 4071f34979SDavid Gibson d-cache-line-size = <32>; 4171f34979SDavid Gibson i-cache-size = <32768>; 4271f34979SDavid Gibson d-cache-size = <32768>; 43c06cf7daSStefan Roese dcr-controller; 44c06cf7daSStefan Roese dcr-access-method = "native"; 45c06cf7daSStefan Roese }; 46c06cf7daSStefan Roese }; 47c06cf7daSStefan Roese 48c06cf7daSStefan Roese memory { 49c06cf7daSStefan Roese device_type = "memory"; 5071f34979SDavid Gibson reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 51c06cf7daSStefan Roese }; 52c06cf7daSStefan Roese 53c06cf7daSStefan Roese UIC0: interrupt-controller0 { 54c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 55c06cf7daSStefan Roese interrupt-controller; 56c06cf7daSStefan Roese cell-index = <0>; 5771f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 58c06cf7daSStefan Roese #address-cells = <0>; 59c06cf7daSStefan Roese #size-cells = <0>; 60c06cf7daSStefan Roese #interrupt-cells = <2>; 61c06cf7daSStefan Roese }; 62c06cf7daSStefan Roese 63c06cf7daSStefan Roese UIC1: interrupt-controller1 { 64c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 65c06cf7daSStefan Roese interrupt-controller; 66c06cf7daSStefan Roese cell-index = <1>; 6771f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 68c06cf7daSStefan Roese #address-cells = <0>; 69c06cf7daSStefan Roese #size-cells = <0>; 70c06cf7daSStefan Roese #interrupt-cells = <2>; 7171f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 72c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 73c06cf7daSStefan Roese }; 74c06cf7daSStefan Roese 75c06cf7daSStefan Roese UIC2: interrupt-controller2 { 76c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 77c06cf7daSStefan Roese interrupt-controller; 78c06cf7daSStefan Roese cell-index = <2>; 7971f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 80c06cf7daSStefan Roese #address-cells = <0>; 81c06cf7daSStefan Roese #size-cells = <0>; 82c06cf7daSStefan Roese #interrupt-cells = <2>; 8371f34979SDavid Gibson interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 84c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 85c06cf7daSStefan Roese }; 86c06cf7daSStefan Roese 87c06cf7daSStefan Roese UIC3: interrupt-controller3 { 88c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 89c06cf7daSStefan Roese interrupt-controller; 90c06cf7daSStefan Roese cell-index = <3>; 9171f34979SDavid Gibson dcr-reg = <0x0f0 0x009>; 92c06cf7daSStefan Roese #address-cells = <0>; 93c06cf7daSStefan Roese #size-cells = <0>; 94c06cf7daSStefan Roese #interrupt-cells = <2>; 9571f34979SDavid Gibson interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 96c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 97c06cf7daSStefan Roese }; 98c06cf7daSStefan Roese 99c06cf7daSStefan Roese SDR0: sdr { 100c06cf7daSStefan Roese compatible = "ibm,sdr-460gt"; 10171f34979SDavid Gibson dcr-reg = <0x00e 0x002>; 102c06cf7daSStefan Roese }; 103c06cf7daSStefan Roese 104c06cf7daSStefan Roese CPR0: cpr { 105c06cf7daSStefan Roese compatible = "ibm,cpr-460gt"; 10671f34979SDavid Gibson dcr-reg = <0x00c 0x002>; 107c06cf7daSStefan Roese }; 108c06cf7daSStefan Roese 109c06cf7daSStefan Roese plb { 110c06cf7daSStefan Roese compatible = "ibm,plb-460gt", "ibm,plb4"; 111c06cf7daSStefan Roese #address-cells = <2>; 112c06cf7daSStefan Roese #size-cells = <1>; 113c06cf7daSStefan Roese ranges; 114c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 115c06cf7daSStefan Roese 116c06cf7daSStefan Roese SDRAM0: sdram { 117c06cf7daSStefan Roese compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; 11871f34979SDavid Gibson dcr-reg = <0x010 0x002>; 119c06cf7daSStefan Roese }; 120c06cf7daSStefan Roese 121c06cf7daSStefan Roese MAL0: mcmal { 122c06cf7daSStefan Roese compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 12371f34979SDavid Gibson dcr-reg = <0x180 0x062>; 124c06cf7daSStefan Roese num-tx-chans = <4>; 12571f34979SDavid Gibson num-rx-chans = <32>; 126c06cf7daSStefan Roese #address-cells = <0>; 127c06cf7daSStefan Roese #size-cells = <0>; 128c06cf7daSStefan Roese interrupt-parent = <&UIC2>; 12971f34979SDavid Gibson interrupts = < /*TXEOB*/ 0x6 0x4 13071f34979SDavid Gibson /*RXEOB*/ 0x7 0x4 13171f34979SDavid Gibson /*SERR*/ 0x3 0x4 13271f34979SDavid Gibson /*TXDE*/ 0x4 0x4 13371f34979SDavid Gibson /*RXDE*/ 0x5 0x4>; 13471f34979SDavid Gibson desc-base-addr-high = <0x8>; 135c06cf7daSStefan Roese }; 136c06cf7daSStefan Roese 137c06cf7daSStefan Roese POB0: opb { 138c06cf7daSStefan Roese compatible = "ibm,opb-460gt", "ibm,opb"; 139c06cf7daSStefan Roese #address-cells = <1>; 140c06cf7daSStefan Roese #size-cells = <1>; 14171f34979SDavid Gibson ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 142c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 143c06cf7daSStefan Roese 144c06cf7daSStefan Roese EBC0: ebc { 145c06cf7daSStefan Roese compatible = "ibm,ebc-460gt", "ibm,ebc"; 14671f34979SDavid Gibson dcr-reg = <0x012 0x002>; 147c06cf7daSStefan Roese #address-cells = <2>; 148c06cf7daSStefan Roese #size-cells = <1>; 149c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1505020231bSStefan Roese /* ranges property is supplied by U-Boot */ 15171f34979SDavid Gibson interrupts = <0x6 0x4>; 152c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 1535020231bSStefan Roese 1545020231bSStefan Roese nor_flash@0,0 { 1555020231bSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 1565020231bSStefan Roese bank-width = <2>; 15771f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 1585020231bSStefan Roese #address-cells = <1>; 1595020231bSStefan Roese #size-cells = <1>; 1605020231bSStefan Roese partition@0 { 1615020231bSStefan Roese label = "kernel"; 16271f34979SDavid Gibson reg = <0x00000000 0x001e0000>; 1635020231bSStefan Roese }; 1645020231bSStefan Roese partition@1e0000 { 1655020231bSStefan Roese label = "dtb"; 16671f34979SDavid Gibson reg = <0x001e0000 0x00020000>; 1675020231bSStefan Roese }; 1685020231bSStefan Roese partition@200000 { 1695020231bSStefan Roese label = "ramdisk"; 17071f34979SDavid Gibson reg = <0x00200000 0x01400000>; 1715020231bSStefan Roese }; 1725020231bSStefan Roese partition@1600000 { 1735020231bSStefan Roese label = "jffs2"; 17471f34979SDavid Gibson reg = <0x01600000 0x00400000>; 1755020231bSStefan Roese }; 1765020231bSStefan Roese partition@1a00000 { 1775020231bSStefan Roese label = "user"; 17871f34979SDavid Gibson reg = <0x01a00000 0x02560000>; 1795020231bSStefan Roese }; 1805020231bSStefan Roese partition@3f60000 { 1815020231bSStefan Roese label = "env"; 18271f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 1835020231bSStefan Roese }; 1845020231bSStefan Roese partition@3fa0000 { 1855020231bSStefan Roese label = "u-boot"; 18671f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 1875020231bSStefan Roese }; 1885020231bSStefan Roese }; 189c06cf7daSStefan Roese }; 190c06cf7daSStefan Roese 191c06cf7daSStefan Roese UART0: serial@ef600300 { 192c06cf7daSStefan Roese device_type = "serial"; 193c06cf7daSStefan Roese compatible = "ns16550"; 19471f34979SDavid Gibson reg = <0xef600300 0x00000008>; 19571f34979SDavid Gibson virtual-reg = <0xef600300>; 196c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 197c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 198c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 19971f34979SDavid Gibson interrupts = <0x1 0x4>; 200c06cf7daSStefan Roese }; 201c06cf7daSStefan Roese 202c06cf7daSStefan Roese UART1: serial@ef600400 { 203c06cf7daSStefan Roese device_type = "serial"; 204c06cf7daSStefan Roese compatible = "ns16550"; 20571f34979SDavid Gibson reg = <0xef600400 0x00000008>; 20671f34979SDavid Gibson virtual-reg = <0xef600400>; 207c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 208c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 209c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 21071f34979SDavid Gibson interrupts = <0x1 0x4>; 211c06cf7daSStefan Roese }; 212c06cf7daSStefan Roese 213c06cf7daSStefan Roese UART2: serial@ef600500 { 214c06cf7daSStefan Roese device_type = "serial"; 215c06cf7daSStefan Roese compatible = "ns16550"; 21671f34979SDavid Gibson reg = <0xef600500 0x00000008>; 21771f34979SDavid Gibson virtual-reg = <0xef600500>; 218c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 219c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 220c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 22171f34979SDavid Gibson interrupts = <0x1d 0x4>; 222c06cf7daSStefan Roese }; 223c06cf7daSStefan Roese 224c06cf7daSStefan Roese UART3: serial@ef600600 { 225c06cf7daSStefan Roese device_type = "serial"; 226c06cf7daSStefan Roese compatible = "ns16550"; 22771f34979SDavid Gibson reg = <0xef600600 0x00000008>; 22871f34979SDavid Gibson virtual-reg = <0xef600600>; 229c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 230c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 231c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 23271f34979SDavid Gibson interrupts = <0x1e 0x4>; 233c06cf7daSStefan Roese }; 234c06cf7daSStefan Roese 235c06cf7daSStefan Roese IIC0: i2c@ef600700 { 236c06cf7daSStefan Roese compatible = "ibm,iic-460gt", "ibm,iic"; 23771f34979SDavid Gibson reg = <0xef600700 0x00000014>; 238c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 23971f34979SDavid Gibson interrupts = <0x2 0x4>; 240c06cf7daSStefan Roese }; 241c06cf7daSStefan Roese 242c06cf7daSStefan Roese IIC1: i2c@ef600800 { 243c06cf7daSStefan Roese compatible = "ibm,iic-460gt", "ibm,iic"; 24471f34979SDavid Gibson reg = <0xef600800 0x00000014>; 245c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 24671f34979SDavid Gibson interrupts = <0x3 0x4>; 247c06cf7daSStefan Roese }; 248c06cf7daSStefan Roese 249c06cf7daSStefan Roese ZMII0: emac-zmii@ef600d00 { 250c06cf7daSStefan Roese compatible = "ibm,zmii-460gt", "ibm,zmii"; 25171f34979SDavid Gibson reg = <0xef600d00 0x0000000c>; 252c06cf7daSStefan Roese }; 253c06cf7daSStefan Roese 254c06cf7daSStefan Roese RGMII0: emac-rgmii@ef601500 { 255c06cf7daSStefan Roese compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 25671f34979SDavid Gibson reg = <0xef601500 0x00000008>; 257c06cf7daSStefan Roese has-mdio; 258c06cf7daSStefan Roese }; 259c06cf7daSStefan Roese 260c06cf7daSStefan Roese RGMII1: emac-rgmii@ef601600 { 261c06cf7daSStefan Roese compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 26271f34979SDavid Gibson reg = <0xef601600 0x00000008>; 263c06cf7daSStefan Roese has-mdio; 264c06cf7daSStefan Roese }; 265c06cf7daSStefan Roese 266c06cf7daSStefan Roese TAH0: emac-tah@ef601350 { 267c06cf7daSStefan Roese compatible = "ibm,tah-460gt", "ibm,tah"; 26871f34979SDavid Gibson reg = <0xef601350 0x00000030>; 269c06cf7daSStefan Roese }; 270c06cf7daSStefan Roese 271c06cf7daSStefan Roese TAH1: emac-tah@ef601450 { 272c06cf7daSStefan Roese compatible = "ibm,tah-460gt", "ibm,tah"; 27371f34979SDavid Gibson reg = <0xef601450 0x00000030>; 274c06cf7daSStefan Roese }; 275c06cf7daSStefan Roese 276c06cf7daSStefan Roese EMAC0: ethernet@ef600e00 { 277c06cf7daSStefan Roese device_type = "network"; 278c06cf7daSStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4"; 279c06cf7daSStefan Roese interrupt-parent = <&EMAC0>; 28071f34979SDavid Gibson interrupts = <0x0 0x1>; 281c06cf7daSStefan Roese #interrupt-cells = <1>; 282c06cf7daSStefan Roese #address-cells = <0>; 283c06cf7daSStefan Roese #size-cells = <0>; 28471f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 28571f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x14 0x4>; 28605781ccdSGrant Erickson reg = <0xef600e00 0x00000074>; 287c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 288c06cf7daSStefan Roese mal-device = <&MAL0>; 289c06cf7daSStefan Roese mal-tx-channel = <0>; 290c06cf7daSStefan Roese mal-rx-channel = <0>; 291c06cf7daSStefan Roese cell-index = <0>; 29271f34979SDavid Gibson max-frame-size = <9000>; 29371f34979SDavid Gibson rx-fifo-size = <4096>; 29471f34979SDavid Gibson tx-fifo-size = <2048>; 295c06cf7daSStefan Roese phy-mode = "rgmii"; 29671f34979SDavid Gibson phy-map = <0x00000000>; 297c06cf7daSStefan Roese rgmii-device = <&RGMII0>; 298c06cf7daSStefan Roese rgmii-channel = <0>; 299c06cf7daSStefan Roese tah-device = <&TAH0>; 300c06cf7daSStefan Roese tah-channel = <0>; 301c06cf7daSStefan Roese has-inverted-stacr-oc; 302c06cf7daSStefan Roese has-new-stacr-staopc; 303c06cf7daSStefan Roese }; 304c06cf7daSStefan Roese 305c06cf7daSStefan Roese EMAC1: ethernet@ef600f00 { 306c06cf7daSStefan Roese device_type = "network"; 307c06cf7daSStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4"; 308c06cf7daSStefan Roese interrupt-parent = <&EMAC1>; 30971f34979SDavid Gibson interrupts = <0x0 0x1>; 310c06cf7daSStefan Roese #interrupt-cells = <1>; 311c06cf7daSStefan Roese #address-cells = <0>; 312c06cf7daSStefan Roese #size-cells = <0>; 31371f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 31471f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x15 0x4>; 31505781ccdSGrant Erickson reg = <0xef600f00 0x00000074>; 316c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 317c06cf7daSStefan Roese mal-device = <&MAL0>; 318c06cf7daSStefan Roese mal-tx-channel = <1>; 319c06cf7daSStefan Roese mal-rx-channel = <8>; 320c06cf7daSStefan Roese cell-index = <1>; 32171f34979SDavid Gibson max-frame-size = <9000>; 32271f34979SDavid Gibson rx-fifo-size = <4096>; 32371f34979SDavid Gibson tx-fifo-size = <2048>; 324c06cf7daSStefan Roese phy-mode = "rgmii"; 32571f34979SDavid Gibson phy-map = <0x00000000>; 326c06cf7daSStefan Roese rgmii-device = <&RGMII0>; 327c06cf7daSStefan Roese rgmii-channel = <1>; 328c06cf7daSStefan Roese tah-device = <&TAH1>; 329a6190a84SStefan Roese tah-channel = <1>; 330c06cf7daSStefan Roese has-inverted-stacr-oc; 331c06cf7daSStefan Roese has-new-stacr-staopc; 332a6190a84SStefan Roese mdio-device = <&EMAC0>; 333c06cf7daSStefan Roese }; 334c06cf7daSStefan Roese 335c06cf7daSStefan Roese EMAC2: ethernet@ef601100 { 336c06cf7daSStefan Roese device_type = "network"; 337c06cf7daSStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4"; 338c06cf7daSStefan Roese interrupt-parent = <&EMAC2>; 33971f34979SDavid Gibson interrupts = <0x0 0x1>; 340c06cf7daSStefan Roese #interrupt-cells = <1>; 341c06cf7daSStefan Roese #address-cells = <0>; 342c06cf7daSStefan Roese #size-cells = <0>; 34371f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 34471f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x16 0x4>; 34505781ccdSGrant Erickson reg = <0xef601100 0x00000074>; 346c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 347c06cf7daSStefan Roese mal-device = <&MAL0>; 348c06cf7daSStefan Roese mal-tx-channel = <2>; 34971f34979SDavid Gibson mal-rx-channel = <16>; 350c06cf7daSStefan Roese cell-index = <2>; 35171f34979SDavid Gibson max-frame-size = <9000>; 35271f34979SDavid Gibson rx-fifo-size = <4096>; 35371f34979SDavid Gibson tx-fifo-size = <2048>; 354c06cf7daSStefan Roese phy-mode = "rgmii"; 35571f34979SDavid Gibson phy-map = <0x00000000>; 356c06cf7daSStefan Roese rgmii-device = <&RGMII1>; 357c06cf7daSStefan Roese rgmii-channel = <0>; 358c06cf7daSStefan Roese has-inverted-stacr-oc; 359c06cf7daSStefan Roese has-new-stacr-staopc; 360a6190a84SStefan Roese mdio-device = <&EMAC0>; 361c06cf7daSStefan Roese }; 362c06cf7daSStefan Roese 363c06cf7daSStefan Roese EMAC3: ethernet@ef601200 { 364c06cf7daSStefan Roese device_type = "network"; 365c06cf7daSStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4"; 366c06cf7daSStefan Roese interrupt-parent = <&EMAC3>; 36771f34979SDavid Gibson interrupts = <0x0 0x1>; 368c06cf7daSStefan Roese #interrupt-cells = <1>; 369c06cf7daSStefan Roese #address-cells = <0>; 370c06cf7daSStefan Roese #size-cells = <0>; 37171f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4 37271f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x17 0x4>; 37305781ccdSGrant Erickson reg = <0xef601200 0x00000074>; 374c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 375c06cf7daSStefan Roese mal-device = <&MAL0>; 376c06cf7daSStefan Roese mal-tx-channel = <3>; 37771f34979SDavid Gibson mal-rx-channel = <24>; 378c06cf7daSStefan Roese cell-index = <3>; 37971f34979SDavid Gibson max-frame-size = <9000>; 38071f34979SDavid Gibson rx-fifo-size = <4096>; 38171f34979SDavid Gibson tx-fifo-size = <2048>; 382c06cf7daSStefan Roese phy-mode = "rgmii"; 38371f34979SDavid Gibson phy-map = <0x00000000>; 384c06cf7daSStefan Roese rgmii-device = <&RGMII1>; 385c06cf7daSStefan Roese rgmii-channel = <1>; 386c06cf7daSStefan Roese has-inverted-stacr-oc; 387c06cf7daSStefan Roese has-new-stacr-staopc; 388a6190a84SStefan Roese mdio-device = <&EMAC0>; 389c06cf7daSStefan Roese }; 390c06cf7daSStefan Roese }; 391c06cf7daSStefan Roese 392c06cf7daSStefan Roese PCIX0: pci@c0ec00000 { 393c06cf7daSStefan Roese device_type = "pci"; 394c06cf7daSStefan Roese #interrupt-cells = <1>; 395c06cf7daSStefan Roese #size-cells = <2>; 396c06cf7daSStefan Roese #address-cells = <3>; 397c06cf7daSStefan Roese compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix"; 398c06cf7daSStefan Roese primary; 399c06cf7daSStefan Roese large-inbound-windows; 400c06cf7daSStefan Roese enable-msi-hole; 40171f34979SDavid Gibson reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 40271f34979SDavid Gibson 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 40371f34979SDavid Gibson 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 40471f34979SDavid Gibson 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 40571f34979SDavid Gibson 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 406c06cf7daSStefan Roese 407c06cf7daSStefan Roese /* Outbound ranges, one memory and one IO, 408c06cf7daSStefan Roese * later cannot be changed 409c06cf7daSStefan Roese */ 41071f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 41171f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 412c06cf7daSStefan Roese 413c06cf7daSStefan Roese /* Inbound 2GB range starting at 0 */ 41471f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 415c06cf7daSStefan Roese 416c06cf7daSStefan Roese /* This drives busses 0 to 0x3f */ 41771f34979SDavid Gibson bus-range = <0x0 0x3f>; 418c06cf7daSStefan Roese 419c06cf7daSStefan Roese /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 42071f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x0>; 42171f34979SDavid Gibson interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; 422c06cf7daSStefan Roese }; 423c06cf7daSStefan Roese 424c06cf7daSStefan Roese PCIE0: pciex@d00000000 { 425c06cf7daSStefan Roese device_type = "pci"; 426c06cf7daSStefan Roese #interrupt-cells = <1>; 427c06cf7daSStefan Roese #size-cells = <2>; 428c06cf7daSStefan Roese #address-cells = <3>; 429c06cf7daSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 430c06cf7daSStefan Roese primary; 43171f34979SDavid Gibson port = <0x0>; /* port number */ 43271f34979SDavid Gibson reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 43371f34979SDavid Gibson 0x0000000c 0x08010000 0x00001000>; /* Registers */ 43471f34979SDavid Gibson dcr-reg = <0x100 0x020>; 43571f34979SDavid Gibson sdr-base = <0x300>; 436c06cf7daSStefan Roese 437c06cf7daSStefan Roese /* Outbound ranges, one memory and one IO, 438c06cf7daSStefan Roese * later cannot be changed 439c06cf7daSStefan Roese */ 44071f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 44171f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 442c06cf7daSStefan Roese 443c06cf7daSStefan Roese /* Inbound 2GB range starting at 0 */ 44471f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 445c06cf7daSStefan Roese 446c06cf7daSStefan Roese /* This drives busses 40 to 0x7f */ 44771f34979SDavid Gibson bus-range = <0x40 0x7f>; 448c06cf7daSStefan Roese 449c06cf7daSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 450c06cf7daSStefan Roese * to invert PCIe legacy interrupts). 451c06cf7daSStefan Roese * We are de-swizzling here because the numbers are actually for 452c06cf7daSStefan Roese * port of the root complex virtual P2P bridge. But I want 453c06cf7daSStefan Roese * to avoid putting a node for it in the tree, so the numbers 454c06cf7daSStefan Roese * below are basically de-swizzled numbers. 455c06cf7daSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 456c06cf7daSStefan Roese */ 45771f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 458c06cf7daSStefan Roese interrupt-map = < 45971f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ 46071f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ 46171f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ 46271f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; 463c06cf7daSStefan Roese }; 464c06cf7daSStefan Roese 465c06cf7daSStefan Roese PCIE1: pciex@d20000000 { 466c06cf7daSStefan Roese device_type = "pci"; 467c06cf7daSStefan Roese #interrupt-cells = <1>; 468c06cf7daSStefan Roese #size-cells = <2>; 469c06cf7daSStefan Roese #address-cells = <3>; 470c06cf7daSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 471c06cf7daSStefan Roese primary; 47271f34979SDavid Gibson port = <0x1>; /* port number */ 47371f34979SDavid Gibson reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 47471f34979SDavid Gibson 0x0000000c 0x08011000 0x00001000>; /* Registers */ 47571f34979SDavid Gibson dcr-reg = <0x120 0x020>; 47671f34979SDavid Gibson sdr-base = <0x340>; 477c06cf7daSStefan Roese 478c06cf7daSStefan Roese /* Outbound ranges, one memory and one IO, 479c06cf7daSStefan Roese * later cannot be changed 480c06cf7daSStefan Roese */ 48171f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 48271f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 483c06cf7daSStefan Roese 484c06cf7daSStefan Roese /* Inbound 2GB range starting at 0 */ 48571f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 486c06cf7daSStefan Roese 487c06cf7daSStefan Roese /* This drives busses 80 to 0xbf */ 48871f34979SDavid Gibson bus-range = <0x80 0xbf>; 489c06cf7daSStefan Roese 490c06cf7daSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 491c06cf7daSStefan Roese * to invert PCIe legacy interrupts). 492c06cf7daSStefan Roese * We are de-swizzling here because the numbers are actually for 493c06cf7daSStefan Roese * port of the root complex virtual P2P bridge. But I want 494c06cf7daSStefan Roese * to avoid putting a node for it in the tree, so the numbers 495c06cf7daSStefan Roese * below are basically de-swizzled numbers. 496c06cf7daSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 497c06cf7daSStefan Roese */ 49871f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 499c06cf7daSStefan Roese interrupt-map = < 50071f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ 50171f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ 50271f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ 50371f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; 504c06cf7daSStefan Roese }; 505c06cf7daSStefan Roese }; 506c06cf7daSStefan Roese}; 507