1c06cf7daSStefan Roese/* 2c06cf7daSStefan Roese * Device Tree Source for AMCC Glacier (460GT) 3c06cf7daSStefan Roese * 4c06cf7daSStefan Roese * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 5c06cf7daSStefan Roese * 6c06cf7daSStefan Roese * This file is licensed under the terms of the GNU General Public 7c06cf7daSStefan Roese * License version 2. This program is licensed "as is" without 8c06cf7daSStefan Roese * any warranty of any kind, whether express or implied. 9c06cf7daSStefan Roese */ 10c06cf7daSStefan Roese 11c06cf7daSStefan Roese/ { 12c06cf7daSStefan Roese #address-cells = <2>; 13c06cf7daSStefan Roese #size-cells = <1>; 14c06cf7daSStefan Roese model = "amcc,glacier"; 15c06cf7daSStefan Roese compatible = "amcc,glacier", "amcc,canyonlands"; 16c06cf7daSStefan Roese dcr-parent = <&/cpus/cpu@0>; 17c06cf7daSStefan Roese 18c06cf7daSStefan Roese aliases { 19c06cf7daSStefan Roese ethernet0 = &EMAC0; 20c06cf7daSStefan Roese ethernet1 = &EMAC1; 21c06cf7daSStefan Roese ethernet2 = &EMAC2; 22c06cf7daSStefan Roese ethernet3 = &EMAC3; 23c06cf7daSStefan Roese serial0 = &UART0; 24c06cf7daSStefan Roese serial1 = &UART1; 25c06cf7daSStefan Roese }; 26c06cf7daSStefan Roese 27c06cf7daSStefan Roese cpus { 28c06cf7daSStefan Roese #address-cells = <1>; 29c06cf7daSStefan Roese #size-cells = <0>; 30c06cf7daSStefan Roese 31c06cf7daSStefan Roese cpu@0 { 32c06cf7daSStefan Roese device_type = "cpu"; 33c06cf7daSStefan Roese model = "PowerPC,460GT"; 34c06cf7daSStefan Roese reg = <0>; 35c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 36c06cf7daSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 37c06cf7daSStefan Roese i-cache-line-size = <20>; 38c06cf7daSStefan Roese d-cache-line-size = <20>; 39c06cf7daSStefan Roese i-cache-size = <8000>; 40c06cf7daSStefan Roese d-cache-size = <8000>; 41c06cf7daSStefan Roese dcr-controller; 42c06cf7daSStefan Roese dcr-access-method = "native"; 43c06cf7daSStefan Roese }; 44c06cf7daSStefan Roese }; 45c06cf7daSStefan Roese 46c06cf7daSStefan Roese memory { 47c06cf7daSStefan Roese device_type = "memory"; 48c06cf7daSStefan Roese reg = <0 0 0>; /* Filled in by U-Boot */ 49c06cf7daSStefan Roese }; 50c06cf7daSStefan Roese 51c06cf7daSStefan Roese UIC0: interrupt-controller0 { 52c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 53c06cf7daSStefan Roese interrupt-controller; 54c06cf7daSStefan Roese cell-index = <0>; 55c06cf7daSStefan Roese dcr-reg = <0c0 009>; 56c06cf7daSStefan Roese #address-cells = <0>; 57c06cf7daSStefan Roese #size-cells = <0>; 58c06cf7daSStefan Roese #interrupt-cells = <2>; 59c06cf7daSStefan Roese }; 60c06cf7daSStefan Roese 61c06cf7daSStefan Roese UIC1: interrupt-controller1 { 62c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 63c06cf7daSStefan Roese interrupt-controller; 64c06cf7daSStefan Roese cell-index = <1>; 65c06cf7daSStefan Roese dcr-reg = <0d0 009>; 66c06cf7daSStefan Roese #address-cells = <0>; 67c06cf7daSStefan Roese #size-cells = <0>; 68c06cf7daSStefan Roese #interrupt-cells = <2>; 69c06cf7daSStefan Roese interrupts = <1e 4 1f 4>; /* cascade */ 70c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 71c06cf7daSStefan Roese }; 72c06cf7daSStefan Roese 73c06cf7daSStefan Roese UIC2: interrupt-controller2 { 74c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 75c06cf7daSStefan Roese interrupt-controller; 76c06cf7daSStefan Roese cell-index = <2>; 77c06cf7daSStefan Roese dcr-reg = <0e0 009>; 78c06cf7daSStefan Roese #address-cells = <0>; 79c06cf7daSStefan Roese #size-cells = <0>; 80c06cf7daSStefan Roese #interrupt-cells = <2>; 81c06cf7daSStefan Roese interrupts = <a 4 b 4>; /* cascade */ 82c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 83c06cf7daSStefan Roese }; 84c06cf7daSStefan Roese 85c06cf7daSStefan Roese UIC3: interrupt-controller3 { 86c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 87c06cf7daSStefan Roese interrupt-controller; 88c06cf7daSStefan Roese cell-index = <3>; 89c06cf7daSStefan Roese dcr-reg = <0f0 009>; 90c06cf7daSStefan Roese #address-cells = <0>; 91c06cf7daSStefan Roese #size-cells = <0>; 92c06cf7daSStefan Roese #interrupt-cells = <2>; 93c06cf7daSStefan Roese interrupts = <10 4 11 4>; /* cascade */ 94c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 95c06cf7daSStefan Roese }; 96c06cf7daSStefan Roese 97c06cf7daSStefan Roese SDR0: sdr { 98c06cf7daSStefan Roese compatible = "ibm,sdr-460gt"; 99c06cf7daSStefan Roese dcr-reg = <00e 002>; 100c06cf7daSStefan Roese }; 101c06cf7daSStefan Roese 102c06cf7daSStefan Roese CPR0: cpr { 103c06cf7daSStefan Roese compatible = "ibm,cpr-460gt"; 104c06cf7daSStefan Roese dcr-reg = <00c 002>; 105c06cf7daSStefan Roese }; 106c06cf7daSStefan Roese 107c06cf7daSStefan Roese plb { 108c06cf7daSStefan Roese compatible = "ibm,plb-460gt", "ibm,plb4"; 109c06cf7daSStefan Roese #address-cells = <2>; 110c06cf7daSStefan Roese #size-cells = <1>; 111c06cf7daSStefan Roese ranges; 112c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 113c06cf7daSStefan Roese 114c06cf7daSStefan Roese SDRAM0: sdram { 115c06cf7daSStefan Roese compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; 116c06cf7daSStefan Roese dcr-reg = <010 2>; 117c06cf7daSStefan Roese }; 118c06cf7daSStefan Roese 119c06cf7daSStefan Roese MAL0: mcmal { 120c06cf7daSStefan Roese compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 121c06cf7daSStefan Roese dcr-reg = <180 62>; 122c06cf7daSStefan Roese num-tx-chans = <4>; 123c06cf7daSStefan Roese num-rx-chans = <20>; 124c06cf7daSStefan Roese #address-cells = <0>; 125c06cf7daSStefan Roese #size-cells = <0>; 126c06cf7daSStefan Roese interrupt-parent = <&UIC2>; 127c06cf7daSStefan Roese interrupts = < /*TXEOB*/ 6 4 128c06cf7daSStefan Roese /*RXEOB*/ 7 4 129c06cf7daSStefan Roese /*SERR*/ 3 4 130c06cf7daSStefan Roese /*TXDE*/ 4 4 131c06cf7daSStefan Roese /*RXDE*/ 5 4>; 132c06cf7daSStefan Roese desc-base-addr-high = <8>; 133c06cf7daSStefan Roese }; 134c06cf7daSStefan Roese 135c06cf7daSStefan Roese POB0: opb { 136c06cf7daSStefan Roese compatible = "ibm,opb-460gt", "ibm,opb"; 137c06cf7daSStefan Roese #address-cells = <1>; 138c06cf7daSStefan Roese #size-cells = <1>; 139c06cf7daSStefan Roese ranges = <b0000000 4 b0000000 50000000>; 140c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 141c06cf7daSStefan Roese 142c06cf7daSStefan Roese EBC0: ebc { 143c06cf7daSStefan Roese compatible = "ibm,ebc-460gt", "ibm,ebc"; 144c06cf7daSStefan Roese dcr-reg = <012 2>; 145c06cf7daSStefan Roese #address-cells = <2>; 146c06cf7daSStefan Roese #size-cells = <1>; 147c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 148c06cf7daSStefan Roese interrupts = <6 4>; 149c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 150c06cf7daSStefan Roese }; 151c06cf7daSStefan Roese 152c06cf7daSStefan Roese UART0: serial@ef600300 { 153c06cf7daSStefan Roese device_type = "serial"; 154c06cf7daSStefan Roese compatible = "ns16550"; 155c06cf7daSStefan Roese reg = <ef600300 8>; 156c06cf7daSStefan Roese virtual-reg = <ef600300>; 157c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 158c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 159c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 160c06cf7daSStefan Roese interrupts = <1 4>; 161c06cf7daSStefan Roese }; 162c06cf7daSStefan Roese 163c06cf7daSStefan Roese UART1: serial@ef600400 { 164c06cf7daSStefan Roese device_type = "serial"; 165c06cf7daSStefan Roese compatible = "ns16550"; 166c06cf7daSStefan Roese reg = <ef600400 8>; 167c06cf7daSStefan Roese virtual-reg = <ef600400>; 168c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 169c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 170c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 171c06cf7daSStefan Roese interrupts = <1 4>; 172c06cf7daSStefan Roese }; 173c06cf7daSStefan Roese 174c06cf7daSStefan Roese UART2: serial@ef600500 { 175c06cf7daSStefan Roese device_type = "serial"; 176c06cf7daSStefan Roese compatible = "ns16550"; 177c06cf7daSStefan Roese reg = <ef600500 8>; 178c06cf7daSStefan Roese virtual-reg = <ef600500>; 179c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 180c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 181c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 182c06cf7daSStefan Roese interrupts = <1d 4>; 183c06cf7daSStefan Roese }; 184c06cf7daSStefan Roese 185c06cf7daSStefan Roese UART3: serial@ef600600 { 186c06cf7daSStefan Roese device_type = "serial"; 187c06cf7daSStefan Roese compatible = "ns16550"; 188c06cf7daSStefan Roese reg = <ef600600 8>; 189c06cf7daSStefan Roese virtual-reg = <ef600600>; 190c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 191c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 192c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 193c06cf7daSStefan Roese interrupts = <1e 4>; 194c06cf7daSStefan Roese }; 195c06cf7daSStefan Roese 196c06cf7daSStefan Roese IIC0: i2c@ef600700 { 197c06cf7daSStefan Roese compatible = "ibm,iic-460gt", "ibm,iic"; 198c06cf7daSStefan Roese reg = <ef600700 14>; 199c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 200c06cf7daSStefan Roese interrupts = <2 4>; 201c06cf7daSStefan Roese }; 202c06cf7daSStefan Roese 203c06cf7daSStefan Roese IIC1: i2c@ef600800 { 204c06cf7daSStefan Roese compatible = "ibm,iic-460gt", "ibm,iic"; 205c06cf7daSStefan Roese reg = <ef600800 14>; 206c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 207c06cf7daSStefan Roese interrupts = <3 4>; 208c06cf7daSStefan Roese }; 209c06cf7daSStefan Roese 210c06cf7daSStefan Roese ZMII0: emac-zmii@ef600d00 { 211c06cf7daSStefan Roese compatible = "ibm,zmii-460gt", "ibm,zmii"; 212c06cf7daSStefan Roese reg = <ef600d00 c>; 213c06cf7daSStefan Roese }; 214c06cf7daSStefan Roese 215c06cf7daSStefan Roese RGMII0: emac-rgmii@ef601500 { 216c06cf7daSStefan Roese compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 217c06cf7daSStefan Roese reg = <ef601500 8>; 218c06cf7daSStefan Roese has-mdio; 219c06cf7daSStefan Roese }; 220c06cf7daSStefan Roese 221c06cf7daSStefan Roese RGMII1: emac-rgmii@ef601600 { 222c06cf7daSStefan Roese compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 223c06cf7daSStefan Roese reg = <ef601600 8>; 224c06cf7daSStefan Roese has-mdio; 225c06cf7daSStefan Roese }; 226c06cf7daSStefan Roese 227c06cf7daSStefan Roese TAH0: emac-tah@ef601350 { 228c06cf7daSStefan Roese compatible = "ibm,tah-460gt", "ibm,tah"; 229c06cf7daSStefan Roese reg = <ef601350 30>; 230c06cf7daSStefan Roese }; 231c06cf7daSStefan Roese 232c06cf7daSStefan Roese TAH1: emac-tah@ef601450 { 233c06cf7daSStefan Roese compatible = "ibm,tah-460gt", "ibm,tah"; 234c06cf7daSStefan Roese reg = <ef601450 30>; 235c06cf7daSStefan Roese }; 236c06cf7daSStefan Roese 237c06cf7daSStefan Roese EMAC0: ethernet@ef600e00 { 238c06cf7daSStefan Roese device_type = "network"; 239c06cf7daSStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4"; 240c06cf7daSStefan Roese interrupt-parent = <&EMAC0>; 241c06cf7daSStefan Roese interrupts = <0 1>; 242c06cf7daSStefan Roese #interrupt-cells = <1>; 243c06cf7daSStefan Roese #address-cells = <0>; 244c06cf7daSStefan Roese #size-cells = <0>; 245c06cf7daSStefan Roese interrupt-map = </*Status*/ 0 &UIC2 10 4 246c06cf7daSStefan Roese /*Wake*/ 1 &UIC2 14 4>; 247c06cf7daSStefan Roese reg = <ef600e00 70>; 248c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 249c06cf7daSStefan Roese mal-device = <&MAL0>; 250c06cf7daSStefan Roese mal-tx-channel = <0>; 251c06cf7daSStefan Roese mal-rx-channel = <0>; 252c06cf7daSStefan Roese cell-index = <0>; 253c06cf7daSStefan Roese max-frame-size = <2328>; 254c06cf7daSStefan Roese rx-fifo-size = <1000>; 255c06cf7daSStefan Roese tx-fifo-size = <800>; 256c06cf7daSStefan Roese phy-mode = "rgmii"; 257c06cf7daSStefan Roese phy-map = <00000000>; 258c06cf7daSStefan Roese rgmii-device = <&RGMII0>; 259c06cf7daSStefan Roese rgmii-channel = <0>; 260c06cf7daSStefan Roese tah-device = <&TAH0>; 261c06cf7daSStefan Roese tah-channel = <0>; 262c06cf7daSStefan Roese has-inverted-stacr-oc; 263c06cf7daSStefan Roese has-new-stacr-staopc; 264c06cf7daSStefan Roese }; 265c06cf7daSStefan Roese 266c06cf7daSStefan Roese EMAC1: ethernet@ef600f00 { 267c06cf7daSStefan Roese device_type = "network"; 268c06cf7daSStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4"; 269c06cf7daSStefan Roese interrupt-parent = <&EMAC1>; 270c06cf7daSStefan Roese interrupts = <0 1>; 271c06cf7daSStefan Roese #interrupt-cells = <1>; 272c06cf7daSStefan Roese #address-cells = <0>; 273c06cf7daSStefan Roese #size-cells = <0>; 274c06cf7daSStefan Roese interrupt-map = </*Status*/ 0 &UIC2 11 4 275c06cf7daSStefan Roese /*Wake*/ 1 &UIC2 15 4>; 276c06cf7daSStefan Roese reg = <ef600f00 70>; 277c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 278c06cf7daSStefan Roese mal-device = <&MAL0>; 279c06cf7daSStefan Roese mal-tx-channel = <1>; 280c06cf7daSStefan Roese mal-rx-channel = <8>; 281c06cf7daSStefan Roese cell-index = <1>; 282c06cf7daSStefan Roese max-frame-size = <2328>; 283c06cf7daSStefan Roese rx-fifo-size = <1000>; 284c06cf7daSStefan Roese tx-fifo-size = <800>; 285c06cf7daSStefan Roese phy-mode = "rgmii"; 286c06cf7daSStefan Roese phy-map = <00000000>; 287c06cf7daSStefan Roese rgmii-device = <&RGMII0>; 288c06cf7daSStefan Roese rgmii-channel = <1>; 289c06cf7daSStefan Roese tah-device = <&TAH1>; 290c06cf7daSStefan Roese tah-channel = <0>; 291c06cf7daSStefan Roese has-inverted-stacr-oc; 292c06cf7daSStefan Roese has-new-stacr-staopc; 293c06cf7daSStefan Roese }; 294c06cf7daSStefan Roese 295c06cf7daSStefan Roese EMAC2: ethernet@ef601100 { 296c06cf7daSStefan Roese device_type = "network"; 297c06cf7daSStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4"; 298c06cf7daSStefan Roese interrupt-parent = <&EMAC2>; 299c06cf7daSStefan Roese interrupts = <0 1>; 300c06cf7daSStefan Roese #interrupt-cells = <1>; 301c06cf7daSStefan Roese #address-cells = <0>; 302c06cf7daSStefan Roese #size-cells = <0>; 303c06cf7daSStefan Roese interrupt-map = </*Status*/ 0 &UIC2 12 4 304c06cf7daSStefan Roese /*Wake*/ 1 &UIC2 16 4>; 305c06cf7daSStefan Roese reg = <ef601100 70>; 306c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 307c06cf7daSStefan Roese mal-device = <&MAL0>; 308c06cf7daSStefan Roese mal-tx-channel = <2>; 309c06cf7daSStefan Roese mal-rx-channel = <10>; 310c06cf7daSStefan Roese cell-index = <2>; 311c06cf7daSStefan Roese max-frame-size = <2328>; 312c06cf7daSStefan Roese rx-fifo-size = <1000>; 313c06cf7daSStefan Roese tx-fifo-size = <800>; 314c06cf7daSStefan Roese phy-mode = "rgmii"; 315c06cf7daSStefan Roese phy-map = <00000000>; 316c06cf7daSStefan Roese rgmii-device = <&RGMII1>; 317c06cf7daSStefan Roese rgmii-channel = <0>; 318c06cf7daSStefan Roese has-inverted-stacr-oc; 319c06cf7daSStefan Roese has-new-stacr-staopc; 320c06cf7daSStefan Roese }; 321c06cf7daSStefan Roese 322c06cf7daSStefan Roese EMAC3: ethernet@ef601200 { 323c06cf7daSStefan Roese device_type = "network"; 324c06cf7daSStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4"; 325c06cf7daSStefan Roese interrupt-parent = <&EMAC3>; 326c06cf7daSStefan Roese interrupts = <0 1>; 327c06cf7daSStefan Roese #interrupt-cells = <1>; 328c06cf7daSStefan Roese #address-cells = <0>; 329c06cf7daSStefan Roese #size-cells = <0>; 330c06cf7daSStefan Roese interrupt-map = </*Status*/ 0 &UIC2 13 4 331c06cf7daSStefan Roese /*Wake*/ 1 &UIC2 17 4>; 332c06cf7daSStefan Roese reg = <ef601200 70>; 333c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 334c06cf7daSStefan Roese mal-device = <&MAL0>; 335c06cf7daSStefan Roese mal-tx-channel = <3>; 336c06cf7daSStefan Roese mal-rx-channel = <18>; 337c06cf7daSStefan Roese cell-index = <3>; 338c06cf7daSStefan Roese max-frame-size = <2328>; 339c06cf7daSStefan Roese rx-fifo-size = <1000>; 340c06cf7daSStefan Roese tx-fifo-size = <800>; 341c06cf7daSStefan Roese phy-mode = "rgmii"; 342c06cf7daSStefan Roese phy-map = <00000000>; 343c06cf7daSStefan Roese rgmii-device = <&RGMII1>; 344c06cf7daSStefan Roese rgmii-channel = <1>; 345c06cf7daSStefan Roese has-inverted-stacr-oc; 346c06cf7daSStefan Roese has-new-stacr-staopc; 347c06cf7daSStefan Roese }; 348c06cf7daSStefan Roese }; 349c06cf7daSStefan Roese 350c06cf7daSStefan Roese PCIX0: pci@c0ec00000 { 351c06cf7daSStefan Roese device_type = "pci"; 352c06cf7daSStefan Roese #interrupt-cells = <1>; 353c06cf7daSStefan Roese #size-cells = <2>; 354c06cf7daSStefan Roese #address-cells = <3>; 355c06cf7daSStefan Roese compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix"; 356c06cf7daSStefan Roese primary; 357c06cf7daSStefan Roese large-inbound-windows; 358c06cf7daSStefan Roese enable-msi-hole; 359c06cf7daSStefan Roese reg = <c 0ec00000 8 /* Config space access */ 360c06cf7daSStefan Roese 0 0 0 /* no IACK cycles */ 361c06cf7daSStefan Roese c 0ed00000 4 /* Special cycles */ 362c06cf7daSStefan Roese c 0ec80000 100 /* Internal registers */ 363c06cf7daSStefan Roese c 0ec80100 fc>; /* Internal messaging registers */ 364c06cf7daSStefan Roese 365c06cf7daSStefan Roese /* Outbound ranges, one memory and one IO, 366c06cf7daSStefan Roese * later cannot be changed 367c06cf7daSStefan Roese */ 368c06cf7daSStefan Roese ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 369c06cf7daSStefan Roese 01000000 0 00000000 0000000c 08000000 0 00010000>; 370c06cf7daSStefan Roese 371c06cf7daSStefan Roese /* Inbound 2GB range starting at 0 */ 372c06cf7daSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 373c06cf7daSStefan Roese 374c06cf7daSStefan Roese /* This drives busses 0 to 0x3f */ 375c06cf7daSStefan Roese bus-range = <0 3f>; 376c06cf7daSStefan Roese 377c06cf7daSStefan Roese /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 378c06cf7daSStefan Roese interrupt-map-mask = <0000 0 0 0>; 379c06cf7daSStefan Roese interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; 380c06cf7daSStefan Roese }; 381c06cf7daSStefan Roese 382c06cf7daSStefan Roese PCIE0: pciex@d00000000 { 383c06cf7daSStefan Roese device_type = "pci"; 384c06cf7daSStefan Roese #interrupt-cells = <1>; 385c06cf7daSStefan Roese #size-cells = <2>; 386c06cf7daSStefan Roese #address-cells = <3>; 387c06cf7daSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 388c06cf7daSStefan Roese primary; 389c06cf7daSStefan Roese port = <0>; /* port number */ 390c06cf7daSStefan Roese reg = <d 00000000 20000000 /* Config space access */ 391c06cf7daSStefan Roese c 08010000 00001000>; /* Registers */ 392c06cf7daSStefan Roese dcr-reg = <100 020>; 393c06cf7daSStefan Roese sdr-base = <300>; 394c06cf7daSStefan Roese 395c06cf7daSStefan Roese /* Outbound ranges, one memory and one IO, 396c06cf7daSStefan Roese * later cannot be changed 397c06cf7daSStefan Roese */ 398c06cf7daSStefan Roese ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 399c06cf7daSStefan Roese 01000000 0 00000000 0000000f 80000000 0 00010000>; 400c06cf7daSStefan Roese 401c06cf7daSStefan Roese /* Inbound 2GB range starting at 0 */ 402c06cf7daSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 403c06cf7daSStefan Roese 404c06cf7daSStefan Roese /* This drives busses 40 to 0x7f */ 405c06cf7daSStefan Roese bus-range = <40 7f>; 406c06cf7daSStefan Roese 407c06cf7daSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 408c06cf7daSStefan Roese * to invert PCIe legacy interrupts). 409c06cf7daSStefan Roese * We are de-swizzling here because the numbers are actually for 410c06cf7daSStefan Roese * port of the root complex virtual P2P bridge. But I want 411c06cf7daSStefan Roese * to avoid putting a node for it in the tree, so the numbers 412c06cf7daSStefan Roese * below are basically de-swizzled numbers. 413c06cf7daSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 414c06cf7daSStefan Roese */ 415c06cf7daSStefan Roese interrupt-map-mask = <0000 0 0 7>; 416c06cf7daSStefan Roese interrupt-map = < 417c06cf7daSStefan Roese 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ 418c06cf7daSStefan Roese 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ 419c06cf7daSStefan Roese 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ 420c06cf7daSStefan Roese 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; 421c06cf7daSStefan Roese }; 422c06cf7daSStefan Roese 423c06cf7daSStefan Roese PCIE1: pciex@d20000000 { 424c06cf7daSStefan Roese device_type = "pci"; 425c06cf7daSStefan Roese #interrupt-cells = <1>; 426c06cf7daSStefan Roese #size-cells = <2>; 427c06cf7daSStefan Roese #address-cells = <3>; 428c06cf7daSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 429c06cf7daSStefan Roese primary; 430c06cf7daSStefan Roese port = <1>; /* port number */ 431c06cf7daSStefan Roese reg = <d 20000000 20000000 /* Config space access */ 432c06cf7daSStefan Roese c 08011000 00001000>; /* Registers */ 433c06cf7daSStefan Roese dcr-reg = <120 020>; 434c06cf7daSStefan Roese sdr-base = <340>; 435c06cf7daSStefan Roese 436c06cf7daSStefan Roese /* Outbound ranges, one memory and one IO, 437c06cf7daSStefan Roese * later cannot be changed 438c06cf7daSStefan Roese */ 439c06cf7daSStefan Roese ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 440c06cf7daSStefan Roese 01000000 0 00000000 0000000f 80010000 0 00010000>; 441c06cf7daSStefan Roese 442c06cf7daSStefan Roese /* Inbound 2GB range starting at 0 */ 443c06cf7daSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 444c06cf7daSStefan Roese 445c06cf7daSStefan Roese /* This drives busses 80 to 0xbf */ 446c06cf7daSStefan Roese bus-range = <80 bf>; 447c06cf7daSStefan Roese 448c06cf7daSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 449c06cf7daSStefan Roese * to invert PCIe legacy interrupts). 450c06cf7daSStefan Roese * We are de-swizzling here because the numbers are actually for 451c06cf7daSStefan Roese * port of the root complex virtual P2P bridge. But I want 452c06cf7daSStefan Roese * to avoid putting a node for it in the tree, so the numbers 453c06cf7daSStefan Roese * below are basically de-swizzled numbers. 454c06cf7daSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 455c06cf7daSStefan Roese */ 456c06cf7daSStefan Roese interrupt-map-mask = <0000 0 0 7>; 457c06cf7daSStefan Roese interrupt-map = < 458c06cf7daSStefan Roese 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ 459c06cf7daSStefan Roese 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ 460c06cf7daSStefan Roese 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ 461c06cf7daSStefan Roese 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; 462c06cf7daSStefan Roese }; 463c06cf7daSStefan Roese }; 464c06cf7daSStefan Roese}; 465