1c06cf7daSStefan Roese/* 2c06cf7daSStefan Roese * Device Tree Source for AMCC Glacier (460GT) 3c06cf7daSStefan Roese * 45a6543e8SStefan Roese * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de> 5c06cf7daSStefan Roese * 6c06cf7daSStefan Roese * This file is licensed under the terms of the GNU General Public 7c06cf7daSStefan Roese * License version 2. This program is licensed "as is" without 8c06cf7daSStefan Roese * any warranty of any kind, whether express or implied. 9c06cf7daSStefan Roese */ 10c06cf7daSStefan Roese 1171f34979SDavid Gibson/dts-v1/; 1271f34979SDavid Gibson 13c06cf7daSStefan Roese/ { 14c06cf7daSStefan Roese #address-cells = <2>; 15c06cf7daSStefan Roese #size-cells = <1>; 16c06cf7daSStefan Roese model = "amcc,glacier"; 17ded563cfSJosh Boyer compatible = "amcc,glacier"; 1871f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 19c06cf7daSStefan Roese 20c06cf7daSStefan Roese aliases { 21c06cf7daSStefan Roese ethernet0 = &EMAC0; 22c06cf7daSStefan Roese ethernet1 = &EMAC1; 23c06cf7daSStefan Roese ethernet2 = &EMAC2; 24c06cf7daSStefan Roese ethernet3 = &EMAC3; 25c06cf7daSStefan Roese serial0 = &UART0; 26c06cf7daSStefan Roese serial1 = &UART1; 27c06cf7daSStefan Roese }; 28c06cf7daSStefan Roese 29c06cf7daSStefan Roese cpus { 30c06cf7daSStefan Roese #address-cells = <1>; 31c06cf7daSStefan Roese #size-cells = <0>; 32c06cf7daSStefan Roese 33c06cf7daSStefan Roese cpu@0 { 34c06cf7daSStefan Roese device_type = "cpu"; 35c06cf7daSStefan Roese model = "PowerPC,460GT"; 3671f34979SDavid Gibson reg = <0x00000000>; 37c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 38c06cf7daSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3971f34979SDavid Gibson i-cache-line-size = <32>; 4071f34979SDavid Gibson d-cache-line-size = <32>; 4171f34979SDavid Gibson i-cache-size = <32768>; 4271f34979SDavid Gibson d-cache-size = <32768>; 43c06cf7daSStefan Roese dcr-controller; 44c06cf7daSStefan Roese dcr-access-method = "native"; 455a6543e8SStefan Roese next-level-cache = <&L2C0>; 46c06cf7daSStefan Roese }; 47c06cf7daSStefan Roese }; 48c06cf7daSStefan Roese 49c06cf7daSStefan Roese memory { 50c06cf7daSStefan Roese device_type = "memory"; 5171f34979SDavid Gibson reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 52c06cf7daSStefan Roese }; 53c06cf7daSStefan Roese 54c06cf7daSStefan Roese UIC0: interrupt-controller0 { 55c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 56c06cf7daSStefan Roese interrupt-controller; 57c06cf7daSStefan Roese cell-index = <0>; 5871f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 59c06cf7daSStefan Roese #address-cells = <0>; 60c06cf7daSStefan Roese #size-cells = <0>; 61c06cf7daSStefan Roese #interrupt-cells = <2>; 62c06cf7daSStefan Roese }; 63c06cf7daSStefan Roese 64c06cf7daSStefan Roese UIC1: interrupt-controller1 { 65c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 66c06cf7daSStefan Roese interrupt-controller; 67c06cf7daSStefan Roese cell-index = <1>; 6871f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 69c06cf7daSStefan Roese #address-cells = <0>; 70c06cf7daSStefan Roese #size-cells = <0>; 71c06cf7daSStefan Roese #interrupt-cells = <2>; 7271f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 73c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 74c06cf7daSStefan Roese }; 75c06cf7daSStefan Roese 76c06cf7daSStefan Roese UIC2: interrupt-controller2 { 77c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 78c06cf7daSStefan Roese interrupt-controller; 79c06cf7daSStefan Roese cell-index = <2>; 8071f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 81c06cf7daSStefan Roese #address-cells = <0>; 82c06cf7daSStefan Roese #size-cells = <0>; 83c06cf7daSStefan Roese #interrupt-cells = <2>; 8471f34979SDavid Gibson interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 85c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 86c06cf7daSStefan Roese }; 87c06cf7daSStefan Roese 88c06cf7daSStefan Roese UIC3: interrupt-controller3 { 89c06cf7daSStefan Roese compatible = "ibm,uic-460gt","ibm,uic"; 90c06cf7daSStefan Roese interrupt-controller; 91c06cf7daSStefan Roese cell-index = <3>; 9271f34979SDavid Gibson dcr-reg = <0x0f0 0x009>; 93c06cf7daSStefan Roese #address-cells = <0>; 94c06cf7daSStefan Roese #size-cells = <0>; 95c06cf7daSStefan Roese #interrupt-cells = <2>; 9671f34979SDavid Gibson interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 97c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 98c06cf7daSStefan Roese }; 99c06cf7daSStefan Roese 100c06cf7daSStefan Roese SDR0: sdr { 101c06cf7daSStefan Roese compatible = "ibm,sdr-460gt"; 10271f34979SDavid Gibson dcr-reg = <0x00e 0x002>; 103c06cf7daSStefan Roese }; 104c06cf7daSStefan Roese 105c06cf7daSStefan Roese CPR0: cpr { 106c06cf7daSStefan Roese compatible = "ibm,cpr-460gt"; 10771f34979SDavid Gibson dcr-reg = <0x00c 0x002>; 108c06cf7daSStefan Roese }; 109c06cf7daSStefan Roese 1105a6543e8SStefan Roese L2C0: l2c { 1115a6543e8SStefan Roese compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; 1125a6543e8SStefan Roese dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 1135a6543e8SStefan Roese 0x030 0x008>; /* L2 cache DCR's */ 1145a6543e8SStefan Roese cache-line-size = <32>; /* 32 bytes */ 1155a6543e8SStefan Roese cache-size = <262144>; /* L2, 256K */ 1165a6543e8SStefan Roese interrupt-parent = <&UIC1>; 1175a6543e8SStefan Roese interrupts = <11 1>; 1185a6543e8SStefan Roese }; 1195a6543e8SStefan Roese 120c06cf7daSStefan Roese plb { 121c06cf7daSStefan Roese compatible = "ibm,plb-460gt", "ibm,plb4"; 122c06cf7daSStefan Roese #address-cells = <2>; 123c06cf7daSStefan Roese #size-cells = <1>; 124c06cf7daSStefan Roese ranges; 125c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 126c06cf7daSStefan Roese 127c06cf7daSStefan Roese SDRAM0: sdram { 128c06cf7daSStefan Roese compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; 12971f34979SDavid Gibson dcr-reg = <0x010 0x002>; 130c06cf7daSStefan Roese }; 131c06cf7daSStefan Roese 1325a6543e8SStefan Roese CRYPTO: crypto@180000 { 1335a6543e8SStefan Roese compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto"; 1345a6543e8SStefan Roese reg = <4 0x00180000 0x80400>; 1355a6543e8SStefan Roese interrupt-parent = <&UIC0>; 1365a6543e8SStefan Roese interrupts = <0x1d 0x4>; 1375a6543e8SStefan Roese }; 1385a6543e8SStefan Roese 139c06cf7daSStefan Roese MAL0: mcmal { 140c06cf7daSStefan Roese compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 14171f34979SDavid Gibson dcr-reg = <0x180 0x062>; 142c06cf7daSStefan Roese num-tx-chans = <4>; 14371f34979SDavid Gibson num-rx-chans = <32>; 144c06cf7daSStefan Roese #address-cells = <0>; 145c06cf7daSStefan Roese #size-cells = <0>; 146c06cf7daSStefan Roese interrupt-parent = <&UIC2>; 14771f34979SDavid Gibson interrupts = < /*TXEOB*/ 0x6 0x4 14871f34979SDavid Gibson /*RXEOB*/ 0x7 0x4 14971f34979SDavid Gibson /*SERR*/ 0x3 0x4 15071f34979SDavid Gibson /*TXDE*/ 0x4 0x4 15171f34979SDavid Gibson /*RXDE*/ 0x5 0x4>; 15271f34979SDavid Gibson desc-base-addr-high = <0x8>; 153c06cf7daSStefan Roese }; 154c06cf7daSStefan Roese 155c06cf7daSStefan Roese POB0: opb { 156c06cf7daSStefan Roese compatible = "ibm,opb-460gt", "ibm,opb"; 157c06cf7daSStefan Roese #address-cells = <1>; 158c06cf7daSStefan Roese #size-cells = <1>; 15971f34979SDavid Gibson ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 160c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 161c06cf7daSStefan Roese 162c06cf7daSStefan Roese EBC0: ebc { 163c06cf7daSStefan Roese compatible = "ibm,ebc-460gt", "ibm,ebc"; 16471f34979SDavid Gibson dcr-reg = <0x012 0x002>; 165c06cf7daSStefan Roese #address-cells = <2>; 166c06cf7daSStefan Roese #size-cells = <1>; 167c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1685020231bSStefan Roese /* ranges property is supplied by U-Boot */ 16971f34979SDavid Gibson interrupts = <0x6 0x4>; 170c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 1715020231bSStefan Roese 1725020231bSStefan Roese nor_flash@0,0 { 1735020231bSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 1745020231bSStefan Roese bank-width = <2>; 17571f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 1765020231bSStefan Roese #address-cells = <1>; 1775020231bSStefan Roese #size-cells = <1>; 1785020231bSStefan Roese partition@0 { 1795020231bSStefan Roese label = "kernel"; 18071f34979SDavid Gibson reg = <0x00000000 0x001e0000>; 1815020231bSStefan Roese }; 1825020231bSStefan Roese partition@1e0000 { 1835020231bSStefan Roese label = "dtb"; 18471f34979SDavid Gibson reg = <0x001e0000 0x00020000>; 1855020231bSStefan Roese }; 1865020231bSStefan Roese partition@200000 { 1875020231bSStefan Roese label = "ramdisk"; 18871f34979SDavid Gibson reg = <0x00200000 0x01400000>; 1895020231bSStefan Roese }; 1905020231bSStefan Roese partition@1600000 { 1915020231bSStefan Roese label = "jffs2"; 19271f34979SDavid Gibson reg = <0x01600000 0x00400000>; 1935020231bSStefan Roese }; 1945020231bSStefan Roese partition@1a00000 { 1955020231bSStefan Roese label = "user"; 19671f34979SDavid Gibson reg = <0x01a00000 0x02560000>; 1975020231bSStefan Roese }; 1985020231bSStefan Roese partition@3f60000 { 1995020231bSStefan Roese label = "env"; 20071f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 2015020231bSStefan Roese }; 2025020231bSStefan Roese partition@3fa0000 { 2035020231bSStefan Roese label = "u-boot"; 20471f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 2055020231bSStefan Roese }; 2065020231bSStefan Roese }; 2075a6543e8SStefan Roese 2085a6543e8SStefan Roese ndfc@3,0 { 2095a6543e8SStefan Roese compatible = "ibm,ndfc"; 2105a6543e8SStefan Roese reg = <0x00000003 0x00000000 0x00002000>; 2115a6543e8SStefan Roese ccr = <0x00001000>; 2125a6543e8SStefan Roese bank-settings = <0x80002222>; 2135a6543e8SStefan Roese #address-cells = <1>; 2145a6543e8SStefan Roese #size-cells = <1>; 2155a6543e8SStefan Roese 2165a6543e8SStefan Roese nand { 2175a6543e8SStefan Roese #address-cells = <1>; 2185a6543e8SStefan Roese #size-cells = <1>; 2195a6543e8SStefan Roese 2205a6543e8SStefan Roese partition@0 { 2215a6543e8SStefan Roese label = "u-boot"; 2225a6543e8SStefan Roese reg = <0x00000000 0x00100000>; 2235a6543e8SStefan Roese }; 2245a6543e8SStefan Roese partition@100000 { 2255a6543e8SStefan Roese label = "user"; 2265a6543e8SStefan Roese reg = <0x00000000 0x03f00000>; 2275a6543e8SStefan Roese }; 2285a6543e8SStefan Roese }; 2295a6543e8SStefan Roese }; 230c06cf7daSStefan Roese }; 231c06cf7daSStefan Roese 232c06cf7daSStefan Roese UART0: serial@ef600300 { 233c06cf7daSStefan Roese device_type = "serial"; 234c06cf7daSStefan Roese compatible = "ns16550"; 23571f34979SDavid Gibson reg = <0xef600300 0x00000008>; 23671f34979SDavid Gibson virtual-reg = <0xef600300>; 237c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 238c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 239c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 24071f34979SDavid Gibson interrupts = <0x1 0x4>; 241c06cf7daSStefan Roese }; 242c06cf7daSStefan Roese 243c06cf7daSStefan Roese UART1: serial@ef600400 { 244c06cf7daSStefan Roese device_type = "serial"; 245c06cf7daSStefan Roese compatible = "ns16550"; 24671f34979SDavid Gibson reg = <0xef600400 0x00000008>; 24771f34979SDavid Gibson virtual-reg = <0xef600400>; 248c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 249c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 250c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 25171f34979SDavid Gibson interrupts = <0x1 0x4>; 252c06cf7daSStefan Roese }; 253c06cf7daSStefan Roese 254c06cf7daSStefan Roese UART2: serial@ef600500 { 255c06cf7daSStefan Roese device_type = "serial"; 256c06cf7daSStefan Roese compatible = "ns16550"; 25771f34979SDavid Gibson reg = <0xef600500 0x00000008>; 25871f34979SDavid Gibson virtual-reg = <0xef600500>; 259c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 260c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 261c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 26271f34979SDavid Gibson interrupts = <0x1d 0x4>; 263c06cf7daSStefan Roese }; 264c06cf7daSStefan Roese 265c06cf7daSStefan Roese UART3: serial@ef600600 { 266c06cf7daSStefan Roese device_type = "serial"; 267c06cf7daSStefan Roese compatible = "ns16550"; 26871f34979SDavid Gibson reg = <0xef600600 0x00000008>; 26971f34979SDavid Gibson virtual-reg = <0xef600600>; 270c06cf7daSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 271c06cf7daSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 272c06cf7daSStefan Roese interrupt-parent = <&UIC1>; 27371f34979SDavid Gibson interrupts = <0x1e 0x4>; 274c06cf7daSStefan Roese }; 275c06cf7daSStefan Roese 276c06cf7daSStefan Roese IIC0: i2c@ef600700 { 277c06cf7daSStefan Roese compatible = "ibm,iic-460gt", "ibm,iic"; 27871f34979SDavid Gibson reg = <0xef600700 0x00000014>; 279c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 28071f34979SDavid Gibson interrupts = <0x2 0x4>; 2815a6543e8SStefan Roese #address-cells = <1>; 2825a6543e8SStefan Roese #size-cells = <0>; 2835a6543e8SStefan Roese rtc@68 { 2845a6543e8SStefan Roese compatible = "stm,m41t80"; 2855a6543e8SStefan Roese reg = <0x68>; 2865a6543e8SStefan Roese interrupt-parent = <&UIC2>; 2875a6543e8SStefan Roese interrupts = <0x19 0x8>; 2885a6543e8SStefan Roese }; 2895a6543e8SStefan Roese sttm@48 { 2905a6543e8SStefan Roese compatible = "ad,ad7414"; 2915a6543e8SStefan Roese reg = <0x48>; 2925a6543e8SStefan Roese interrupt-parent = <&UIC1>; 2935a6543e8SStefan Roese interrupts = <0x14 0x8>; 2945a6543e8SStefan Roese }; 295c06cf7daSStefan Roese }; 296c06cf7daSStefan Roese 297c06cf7daSStefan Roese IIC1: i2c@ef600800 { 298c06cf7daSStefan Roese compatible = "ibm,iic-460gt", "ibm,iic"; 29971f34979SDavid Gibson reg = <0xef600800 0x00000014>; 300c06cf7daSStefan Roese interrupt-parent = <&UIC0>; 30171f34979SDavid Gibson interrupts = <0x3 0x4>; 302c06cf7daSStefan Roese }; 303c06cf7daSStefan Roese 304c06cf7daSStefan Roese ZMII0: emac-zmii@ef600d00 { 305c06cf7daSStefan Roese compatible = "ibm,zmii-460gt", "ibm,zmii"; 30671f34979SDavid Gibson reg = <0xef600d00 0x0000000c>; 307c06cf7daSStefan Roese }; 308c06cf7daSStefan Roese 309c06cf7daSStefan Roese RGMII0: emac-rgmii@ef601500 { 310c06cf7daSStefan Roese compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 31171f34979SDavid Gibson reg = <0xef601500 0x00000008>; 312c06cf7daSStefan Roese has-mdio; 313c06cf7daSStefan Roese }; 314c06cf7daSStefan Roese 315c06cf7daSStefan Roese RGMII1: emac-rgmii@ef601600 { 316c06cf7daSStefan Roese compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 31771f34979SDavid Gibson reg = <0xef601600 0x00000008>; 318c06cf7daSStefan Roese has-mdio; 319c06cf7daSStefan Roese }; 320c06cf7daSStefan Roese 321c06cf7daSStefan Roese TAH0: emac-tah@ef601350 { 322c06cf7daSStefan Roese compatible = "ibm,tah-460gt", "ibm,tah"; 32371f34979SDavid Gibson reg = <0xef601350 0x00000030>; 324c06cf7daSStefan Roese }; 325c06cf7daSStefan Roese 326c06cf7daSStefan Roese TAH1: emac-tah@ef601450 { 327c06cf7daSStefan Roese compatible = "ibm,tah-460gt", "ibm,tah"; 32871f34979SDavid Gibson reg = <0xef601450 0x00000030>; 329c06cf7daSStefan Roese }; 330c06cf7daSStefan Roese 331c06cf7daSStefan Roese EMAC0: ethernet@ef600e00 { 332c06cf7daSStefan Roese device_type = "network"; 3335a6543e8SStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4sync"; 334c06cf7daSStefan Roese interrupt-parent = <&EMAC0>; 33571f34979SDavid Gibson interrupts = <0x0 0x1>; 336c06cf7daSStefan Roese #interrupt-cells = <1>; 337c06cf7daSStefan Roese #address-cells = <0>; 338c06cf7daSStefan Roese #size-cells = <0>; 33971f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 34071f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x14 0x4>; 3415a6543e8SStefan Roese reg = <0xef600e00 0x000000c4>; 342c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 343c06cf7daSStefan Roese mal-device = <&MAL0>; 344c06cf7daSStefan Roese mal-tx-channel = <0>; 345c06cf7daSStefan Roese mal-rx-channel = <0>; 346c06cf7daSStefan Roese cell-index = <0>; 34771f34979SDavid Gibson max-frame-size = <9000>; 34871f34979SDavid Gibson rx-fifo-size = <4096>; 34971f34979SDavid Gibson tx-fifo-size = <2048>; 350835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 351c06cf7daSStefan Roese phy-mode = "rgmii"; 35271f34979SDavid Gibson phy-map = <0x00000000>; 353c06cf7daSStefan Roese rgmii-device = <&RGMII0>; 354c06cf7daSStefan Roese rgmii-channel = <0>; 355c06cf7daSStefan Roese tah-device = <&TAH0>; 356c06cf7daSStefan Roese tah-channel = <0>; 357c06cf7daSStefan Roese has-inverted-stacr-oc; 358c06cf7daSStefan Roese has-new-stacr-staopc; 359c06cf7daSStefan Roese }; 360c06cf7daSStefan Roese 361c06cf7daSStefan Roese EMAC1: ethernet@ef600f00 { 362c06cf7daSStefan Roese device_type = "network"; 3635a6543e8SStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4sync"; 364c06cf7daSStefan Roese interrupt-parent = <&EMAC1>; 36571f34979SDavid Gibson interrupts = <0x0 0x1>; 366c06cf7daSStefan Roese #interrupt-cells = <1>; 367c06cf7daSStefan Roese #address-cells = <0>; 368c06cf7daSStefan Roese #size-cells = <0>; 36971f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 37071f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x15 0x4>; 3715a6543e8SStefan Roese reg = <0xef600f00 0x000000c4>; 372c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 373c06cf7daSStefan Roese mal-device = <&MAL0>; 374c06cf7daSStefan Roese mal-tx-channel = <1>; 375c06cf7daSStefan Roese mal-rx-channel = <8>; 376c06cf7daSStefan Roese cell-index = <1>; 37771f34979SDavid Gibson max-frame-size = <9000>; 37871f34979SDavid Gibson rx-fifo-size = <4096>; 37971f34979SDavid Gibson tx-fifo-size = <2048>; 380835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 381c06cf7daSStefan Roese phy-mode = "rgmii"; 38271f34979SDavid Gibson phy-map = <0x00000000>; 383c06cf7daSStefan Roese rgmii-device = <&RGMII0>; 384c06cf7daSStefan Roese rgmii-channel = <1>; 385c06cf7daSStefan Roese tah-device = <&TAH1>; 386a6190a84SStefan Roese tah-channel = <1>; 387c06cf7daSStefan Roese has-inverted-stacr-oc; 388c06cf7daSStefan Roese has-new-stacr-staopc; 389a6190a84SStefan Roese mdio-device = <&EMAC0>; 390c06cf7daSStefan Roese }; 391c06cf7daSStefan Roese 392c06cf7daSStefan Roese EMAC2: ethernet@ef601100 { 393c06cf7daSStefan Roese device_type = "network"; 3945a6543e8SStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4sync"; 395c06cf7daSStefan Roese interrupt-parent = <&EMAC2>; 39671f34979SDavid Gibson interrupts = <0x0 0x1>; 397c06cf7daSStefan Roese #interrupt-cells = <1>; 398c06cf7daSStefan Roese #address-cells = <0>; 399c06cf7daSStefan Roese #size-cells = <0>; 40071f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 40171f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x16 0x4>; 4025a6543e8SStefan Roese reg = <0xef601100 0x000000c4>; 403c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 404c06cf7daSStefan Roese mal-device = <&MAL0>; 405c06cf7daSStefan Roese mal-tx-channel = <2>; 40671f34979SDavid Gibson mal-rx-channel = <16>; 407c06cf7daSStefan Roese cell-index = <2>; 40871f34979SDavid Gibson max-frame-size = <9000>; 40971f34979SDavid Gibson rx-fifo-size = <4096>; 41071f34979SDavid Gibson tx-fifo-size = <2048>; 411835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 412835ad8e7SDave Mitchell tx-fifo-size-gige = <16384>; /* emac2&3 only */ 413c06cf7daSStefan Roese phy-mode = "rgmii"; 41471f34979SDavid Gibson phy-map = <0x00000000>; 415c06cf7daSStefan Roese rgmii-device = <&RGMII1>; 416c06cf7daSStefan Roese rgmii-channel = <0>; 417c06cf7daSStefan Roese has-inverted-stacr-oc; 418c06cf7daSStefan Roese has-new-stacr-staopc; 419a6190a84SStefan Roese mdio-device = <&EMAC0>; 420c06cf7daSStefan Roese }; 421c06cf7daSStefan Roese 422c06cf7daSStefan Roese EMAC3: ethernet@ef601200 { 423c06cf7daSStefan Roese device_type = "network"; 4245a6543e8SStefan Roese compatible = "ibm,emac-460gt", "ibm,emac4sync"; 425c06cf7daSStefan Roese interrupt-parent = <&EMAC3>; 42671f34979SDavid Gibson interrupts = <0x0 0x1>; 427c06cf7daSStefan Roese #interrupt-cells = <1>; 428c06cf7daSStefan Roese #address-cells = <0>; 429c06cf7daSStefan Roese #size-cells = <0>; 43071f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4 43171f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x17 0x4>; 4325a6543e8SStefan Roese reg = <0xef601200 0x000000c4>; 433c06cf7daSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 434c06cf7daSStefan Roese mal-device = <&MAL0>; 435c06cf7daSStefan Roese mal-tx-channel = <3>; 43671f34979SDavid Gibson mal-rx-channel = <24>; 437c06cf7daSStefan Roese cell-index = <3>; 43871f34979SDavid Gibson max-frame-size = <9000>; 43971f34979SDavid Gibson rx-fifo-size = <4096>; 44071f34979SDavid Gibson tx-fifo-size = <2048>; 441835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 442835ad8e7SDave Mitchell tx-fifo-size-gige = <16384>; /* emac2&3 only */ 443c06cf7daSStefan Roese phy-mode = "rgmii"; 44471f34979SDavid Gibson phy-map = <0x00000000>; 445c06cf7daSStefan Roese rgmii-device = <&RGMII1>; 446c06cf7daSStefan Roese rgmii-channel = <1>; 447c06cf7daSStefan Roese has-inverted-stacr-oc; 448c06cf7daSStefan Roese has-new-stacr-staopc; 449a6190a84SStefan Roese mdio-device = <&EMAC0>; 450c06cf7daSStefan Roese }; 451c06cf7daSStefan Roese }; 452c06cf7daSStefan Roese 453c06cf7daSStefan Roese PCIX0: pci@c0ec00000 { 454c06cf7daSStefan Roese device_type = "pci"; 455c06cf7daSStefan Roese #interrupt-cells = <1>; 456c06cf7daSStefan Roese #size-cells = <2>; 457c06cf7daSStefan Roese #address-cells = <3>; 458c06cf7daSStefan Roese compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix"; 459c06cf7daSStefan Roese primary; 460c06cf7daSStefan Roese large-inbound-windows; 461c06cf7daSStefan Roese enable-msi-hole; 46271f34979SDavid Gibson reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 46371f34979SDavid Gibson 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 46471f34979SDavid Gibson 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 46571f34979SDavid Gibson 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 46671f34979SDavid Gibson 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 467c06cf7daSStefan Roese 468c06cf7daSStefan Roese /* Outbound ranges, one memory and one IO, 469c06cf7daSStefan Roese * later cannot be changed 470c06cf7daSStefan Roese */ 47171f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 4725a6543e8SStefan Roese 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 47371f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 474c06cf7daSStefan Roese 475c06cf7daSStefan Roese /* Inbound 2GB range starting at 0 */ 47671f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 477c06cf7daSStefan Roese 478c06cf7daSStefan Roese /* This drives busses 0 to 0x3f */ 47971f34979SDavid Gibson bus-range = <0x0 0x3f>; 480c06cf7daSStefan Roese 481c06cf7daSStefan Roese /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 48271f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x0>; 48371f34979SDavid Gibson interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; 484c06cf7daSStefan Roese }; 485c06cf7daSStefan Roese 486c06cf7daSStefan Roese PCIE0: pciex@d00000000 { 487c06cf7daSStefan Roese device_type = "pci"; 488c06cf7daSStefan Roese #interrupt-cells = <1>; 489c06cf7daSStefan Roese #size-cells = <2>; 490c06cf7daSStefan Roese #address-cells = <3>; 491c06cf7daSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 492c06cf7daSStefan Roese primary; 49371f34979SDavid Gibson port = <0x0>; /* port number */ 49471f34979SDavid Gibson reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 49571f34979SDavid Gibson 0x0000000c 0x08010000 0x00001000>; /* Registers */ 49671f34979SDavid Gibson dcr-reg = <0x100 0x020>; 49771f34979SDavid Gibson sdr-base = <0x300>; 498c06cf7daSStefan Roese 499c06cf7daSStefan Roese /* Outbound ranges, one memory and one IO, 500c06cf7daSStefan Roese * later cannot be changed 501c06cf7daSStefan Roese */ 50271f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 5035a6543e8SStefan Roese 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 50471f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 505c06cf7daSStefan Roese 506c06cf7daSStefan Roese /* Inbound 2GB range starting at 0 */ 50771f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 508c06cf7daSStefan Roese 509c06cf7daSStefan Roese /* This drives busses 40 to 0x7f */ 51071f34979SDavid Gibson bus-range = <0x40 0x7f>; 511c06cf7daSStefan Roese 512c06cf7daSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 513c06cf7daSStefan Roese * to invert PCIe legacy interrupts). 514c06cf7daSStefan Roese * We are de-swizzling here because the numbers are actually for 515c06cf7daSStefan Roese * port of the root complex virtual P2P bridge. But I want 516c06cf7daSStefan Roese * to avoid putting a node for it in the tree, so the numbers 517c06cf7daSStefan Roese * below are basically de-swizzled numbers. 518c06cf7daSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 519c06cf7daSStefan Roese */ 52071f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 521c06cf7daSStefan Roese interrupt-map = < 52271f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ 52371f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ 52471f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ 52571f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; 526c06cf7daSStefan Roese }; 527c06cf7daSStefan Roese 528c06cf7daSStefan Roese PCIE1: pciex@d20000000 { 529c06cf7daSStefan Roese device_type = "pci"; 530c06cf7daSStefan Roese #interrupt-cells = <1>; 531c06cf7daSStefan Roese #size-cells = <2>; 532c06cf7daSStefan Roese #address-cells = <3>; 533c06cf7daSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 534c06cf7daSStefan Roese primary; 53571f34979SDavid Gibson port = <0x1>; /* port number */ 53671f34979SDavid Gibson reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 53771f34979SDavid Gibson 0x0000000c 0x08011000 0x00001000>; /* Registers */ 53871f34979SDavid Gibson dcr-reg = <0x120 0x020>; 53971f34979SDavid Gibson sdr-base = <0x340>; 540c06cf7daSStefan Roese 541c06cf7daSStefan Roese /* Outbound ranges, one memory and one IO, 542c06cf7daSStefan Roese * later cannot be changed 543c06cf7daSStefan Roese */ 54471f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 5455a6543e8SStefan Roese 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 54671f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 547c06cf7daSStefan Roese 548c06cf7daSStefan Roese /* Inbound 2GB range starting at 0 */ 54971f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 550c06cf7daSStefan Roese 551c06cf7daSStefan Roese /* This drives busses 80 to 0xbf */ 55271f34979SDavid Gibson bus-range = <0x80 0xbf>; 553c06cf7daSStefan Roese 554c06cf7daSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 555c06cf7daSStefan Roese * to invert PCIe legacy interrupts). 556c06cf7daSStefan Roese * We are de-swizzling here because the numbers are actually for 557c06cf7daSStefan Roese * port of the root complex virtual P2P bridge. But I want 558c06cf7daSStefan Roese * to avoid putting a node for it in the tree, so the numbers 559c06cf7daSStefan Roese * below are basically de-swizzled numbers. 560c06cf7daSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 561c06cf7daSStefan Roese */ 56271f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 563c06cf7daSStefan Roese interrupt-map = < 56471f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ 56571f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ 56671f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ 56771f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; 568c06cf7daSStefan Roese }; 569c06cf7daSStefan Roese }; 570c06cf7daSStefan Roese}; 571