xref: /openbmc/linux/arch/powerpc/boot/dts/glacier.dts (revision 5020231b)
1c06cf7daSStefan Roese/*
2c06cf7daSStefan Roese * Device Tree Source for AMCC Glacier (460GT)
3c06cf7daSStefan Roese *
4c06cf7daSStefan Roese * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5c06cf7daSStefan Roese *
6c06cf7daSStefan Roese * This file is licensed under the terms of the GNU General Public
7c06cf7daSStefan Roese * License version 2.  This program is licensed "as is" without
8c06cf7daSStefan Roese * any warranty of any kind, whether express or implied.
9c06cf7daSStefan Roese */
10c06cf7daSStefan Roese
11c06cf7daSStefan Roese/ {
12c06cf7daSStefan Roese	#address-cells = <2>;
13c06cf7daSStefan Roese	#size-cells = <1>;
14c06cf7daSStefan Roese	model = "amcc,glacier";
15c06cf7daSStefan Roese	compatible = "amcc,glacier", "amcc,canyonlands";
16c06cf7daSStefan Roese	dcr-parent = <&/cpus/cpu@0>;
17c06cf7daSStefan Roese
18c06cf7daSStefan Roese	aliases {
19c06cf7daSStefan Roese		ethernet0 = &EMAC0;
20c06cf7daSStefan Roese		ethernet1 = &EMAC1;
21c06cf7daSStefan Roese		ethernet2 = &EMAC2;
22c06cf7daSStefan Roese		ethernet3 = &EMAC3;
23c06cf7daSStefan Roese		serial0 = &UART0;
24c06cf7daSStefan Roese		serial1 = &UART1;
25c06cf7daSStefan Roese	};
26c06cf7daSStefan Roese
27c06cf7daSStefan Roese	cpus {
28c06cf7daSStefan Roese		#address-cells = <1>;
29c06cf7daSStefan Roese		#size-cells = <0>;
30c06cf7daSStefan Roese
31c06cf7daSStefan Roese		cpu@0 {
32c06cf7daSStefan Roese			device_type = "cpu";
33c06cf7daSStefan Roese			model = "PowerPC,460GT";
34c06cf7daSStefan Roese			reg = <0>;
35c06cf7daSStefan Roese			clock-frequency = <0>; /* Filled in by U-Boot */
36c06cf7daSStefan Roese			timebase-frequency = <0>; /* Filled in by U-Boot */
37c06cf7daSStefan Roese			i-cache-line-size = <20>;
38c06cf7daSStefan Roese			d-cache-line-size = <20>;
39c06cf7daSStefan Roese			i-cache-size = <8000>;
40c06cf7daSStefan Roese			d-cache-size = <8000>;
41c06cf7daSStefan Roese			dcr-controller;
42c06cf7daSStefan Roese			dcr-access-method = "native";
43c06cf7daSStefan Roese		};
44c06cf7daSStefan Roese	};
45c06cf7daSStefan Roese
46c06cf7daSStefan Roese	memory {
47c06cf7daSStefan Roese		device_type = "memory";
48c06cf7daSStefan Roese		reg = <0 0 0>; /* Filled in by U-Boot */
49c06cf7daSStefan Roese	};
50c06cf7daSStefan Roese
51c06cf7daSStefan Roese	UIC0: interrupt-controller0 {
52c06cf7daSStefan Roese		compatible = "ibm,uic-460gt","ibm,uic";
53c06cf7daSStefan Roese		interrupt-controller;
54c06cf7daSStefan Roese		cell-index = <0>;
55c06cf7daSStefan Roese		dcr-reg = <0c0 009>;
56c06cf7daSStefan Roese		#address-cells = <0>;
57c06cf7daSStefan Roese		#size-cells = <0>;
58c06cf7daSStefan Roese		#interrupt-cells = <2>;
59c06cf7daSStefan Roese	};
60c06cf7daSStefan Roese
61c06cf7daSStefan Roese	UIC1: interrupt-controller1 {
62c06cf7daSStefan Roese		compatible = "ibm,uic-460gt","ibm,uic";
63c06cf7daSStefan Roese		interrupt-controller;
64c06cf7daSStefan Roese		cell-index = <1>;
65c06cf7daSStefan Roese		dcr-reg = <0d0 009>;
66c06cf7daSStefan Roese		#address-cells = <0>;
67c06cf7daSStefan Roese		#size-cells = <0>;
68c06cf7daSStefan Roese		#interrupt-cells = <2>;
69c06cf7daSStefan Roese		interrupts = <1e 4 1f 4>; /* cascade */
70c06cf7daSStefan Roese		interrupt-parent = <&UIC0>;
71c06cf7daSStefan Roese	};
72c06cf7daSStefan Roese
73c06cf7daSStefan Roese	UIC2: interrupt-controller2 {
74c06cf7daSStefan Roese		compatible = "ibm,uic-460gt","ibm,uic";
75c06cf7daSStefan Roese		interrupt-controller;
76c06cf7daSStefan Roese		cell-index = <2>;
77c06cf7daSStefan Roese		dcr-reg = <0e0 009>;
78c06cf7daSStefan Roese		#address-cells = <0>;
79c06cf7daSStefan Roese		#size-cells = <0>;
80c06cf7daSStefan Roese		#interrupt-cells = <2>;
81c06cf7daSStefan Roese		interrupts = <a 4 b 4>; /* cascade */
82c06cf7daSStefan Roese		interrupt-parent = <&UIC0>;
83c06cf7daSStefan Roese	};
84c06cf7daSStefan Roese
85c06cf7daSStefan Roese	UIC3: interrupt-controller3 {
86c06cf7daSStefan Roese		compatible = "ibm,uic-460gt","ibm,uic";
87c06cf7daSStefan Roese		interrupt-controller;
88c06cf7daSStefan Roese		cell-index = <3>;
89c06cf7daSStefan Roese		dcr-reg = <0f0 009>;
90c06cf7daSStefan Roese		#address-cells = <0>;
91c06cf7daSStefan Roese		#size-cells = <0>;
92c06cf7daSStefan Roese		#interrupt-cells = <2>;
93c06cf7daSStefan Roese		interrupts = <10 4 11 4>; /* cascade */
94c06cf7daSStefan Roese		interrupt-parent = <&UIC0>;
95c06cf7daSStefan Roese	};
96c06cf7daSStefan Roese
97c06cf7daSStefan Roese	SDR0: sdr {
98c06cf7daSStefan Roese		compatible = "ibm,sdr-460gt";
99c06cf7daSStefan Roese		dcr-reg = <00e 002>;
100c06cf7daSStefan Roese	};
101c06cf7daSStefan Roese
102c06cf7daSStefan Roese	CPR0: cpr {
103c06cf7daSStefan Roese		compatible = "ibm,cpr-460gt";
104c06cf7daSStefan Roese		dcr-reg = <00c 002>;
105c06cf7daSStefan Roese	};
106c06cf7daSStefan Roese
107c06cf7daSStefan Roese	plb {
108c06cf7daSStefan Roese		compatible = "ibm,plb-460gt", "ibm,plb4";
109c06cf7daSStefan Roese		#address-cells = <2>;
110c06cf7daSStefan Roese		#size-cells = <1>;
111c06cf7daSStefan Roese		ranges;
112c06cf7daSStefan Roese		clock-frequency = <0>; /* Filled in by U-Boot */
113c06cf7daSStefan Roese
114c06cf7daSStefan Roese		SDRAM0: sdram {
115c06cf7daSStefan Roese			compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
116c06cf7daSStefan Roese			dcr-reg = <010 2>;
117c06cf7daSStefan Roese		};
118c06cf7daSStefan Roese
119c06cf7daSStefan Roese		MAL0: mcmal {
120c06cf7daSStefan Roese			compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
121c06cf7daSStefan Roese			dcr-reg = <180 62>;
122c06cf7daSStefan Roese			num-tx-chans = <4>;
123c06cf7daSStefan Roese			num-rx-chans = <20>;
124c06cf7daSStefan Roese			#address-cells = <0>;
125c06cf7daSStefan Roese			#size-cells = <0>;
126c06cf7daSStefan Roese			interrupt-parent = <&UIC2>;
127c06cf7daSStefan Roese			interrupts = <	/*TXEOB*/ 6 4
128c06cf7daSStefan Roese					/*RXEOB*/ 7 4
129c06cf7daSStefan Roese					/*SERR*/  3 4
130c06cf7daSStefan Roese					/*TXDE*/  4 4
131c06cf7daSStefan Roese					/*RXDE*/  5 4>;
132c06cf7daSStefan Roese			desc-base-addr-high = <8>;
133c06cf7daSStefan Roese		};
134c06cf7daSStefan Roese
135c06cf7daSStefan Roese		POB0: opb {
136c06cf7daSStefan Roese			compatible = "ibm,opb-460gt", "ibm,opb";
137c06cf7daSStefan Roese			#address-cells = <1>;
138c06cf7daSStefan Roese			#size-cells = <1>;
139c06cf7daSStefan Roese			ranges = <b0000000 4 b0000000 50000000>;
140c06cf7daSStefan Roese			clock-frequency = <0>; /* Filled in by U-Boot */
141c06cf7daSStefan Roese
142c06cf7daSStefan Roese			EBC0: ebc {
143c06cf7daSStefan Roese				compatible = "ibm,ebc-460gt", "ibm,ebc";
144c06cf7daSStefan Roese				dcr-reg = <012 2>;
145c06cf7daSStefan Roese				#address-cells = <2>;
146c06cf7daSStefan Roese				#size-cells = <1>;
147c06cf7daSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
1485020231bSStefan Roese				/* ranges property is supplied by U-Boot */
149c06cf7daSStefan Roese				interrupts = <6 4>;
150c06cf7daSStefan Roese				interrupt-parent = <&UIC1>;
1515020231bSStefan Roese
1525020231bSStefan Roese				nor_flash@0,0 {
1535020231bSStefan Roese					compatible = "amd,s29gl512n", "cfi-flash";
1545020231bSStefan Roese					bank-width = <2>;
1555020231bSStefan Roese					reg = <0 000000 4000000>;
1565020231bSStefan Roese					#address-cells = <1>;
1575020231bSStefan Roese					#size-cells = <1>;
1585020231bSStefan Roese					partition@0 {
1595020231bSStefan Roese						label = "kernel";
1605020231bSStefan Roese						reg = <0 1e0000>;
1615020231bSStefan Roese					};
1625020231bSStefan Roese					partition@1e0000 {
1635020231bSStefan Roese						label = "dtb";
1645020231bSStefan Roese						reg = <1e0000 20000>;
1655020231bSStefan Roese					};
1665020231bSStefan Roese					partition@200000 {
1675020231bSStefan Roese						label = "ramdisk";
1685020231bSStefan Roese						reg = <200000 1400000>;
1695020231bSStefan Roese					};
1705020231bSStefan Roese					partition@1600000 {
1715020231bSStefan Roese						label = "jffs2";
1725020231bSStefan Roese						reg = <1600000 400000>;
1735020231bSStefan Roese					};
1745020231bSStefan Roese					partition@1a00000 {
1755020231bSStefan Roese						label = "user";
1765020231bSStefan Roese						reg = <1a00000 2560000>;
1775020231bSStefan Roese					};
1785020231bSStefan Roese					partition@3f60000 {
1795020231bSStefan Roese						label = "env";
1805020231bSStefan Roese						reg = <3f60000 40000>;
1815020231bSStefan Roese					};
1825020231bSStefan Roese					partition@3fa0000 {
1835020231bSStefan Roese						label = "u-boot";
1845020231bSStefan Roese						reg = <3fa0000 60000>;
1855020231bSStefan Roese					};
1865020231bSStefan Roese				};
187c06cf7daSStefan Roese			};
188c06cf7daSStefan Roese
189c06cf7daSStefan Roese			UART0: serial@ef600300 {
190c06cf7daSStefan Roese				device_type = "serial";
191c06cf7daSStefan Roese				compatible = "ns16550";
192c06cf7daSStefan Roese				reg = <ef600300 8>;
193c06cf7daSStefan Roese				virtual-reg = <ef600300>;
194c06cf7daSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
195c06cf7daSStefan Roese				current-speed = <0>; /* Filled in by U-Boot */
196c06cf7daSStefan Roese				interrupt-parent = <&UIC1>;
197c06cf7daSStefan Roese				interrupts = <1 4>;
198c06cf7daSStefan Roese			};
199c06cf7daSStefan Roese
200c06cf7daSStefan Roese			UART1: serial@ef600400 {
201c06cf7daSStefan Roese				device_type = "serial";
202c06cf7daSStefan Roese				compatible = "ns16550";
203c06cf7daSStefan Roese				reg = <ef600400 8>;
204c06cf7daSStefan Roese				virtual-reg = <ef600400>;
205c06cf7daSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
206c06cf7daSStefan Roese				current-speed = <0>; /* Filled in by U-Boot */
207c06cf7daSStefan Roese				interrupt-parent = <&UIC0>;
208c06cf7daSStefan Roese				interrupts = <1 4>;
209c06cf7daSStefan Roese			};
210c06cf7daSStefan Roese
211c06cf7daSStefan Roese			UART2: serial@ef600500 {
212c06cf7daSStefan Roese				device_type = "serial";
213c06cf7daSStefan Roese				compatible = "ns16550";
214c06cf7daSStefan Roese				reg = <ef600500 8>;
215c06cf7daSStefan Roese				virtual-reg = <ef600500>;
216c06cf7daSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
217c06cf7daSStefan Roese				current-speed = <0>; /* Filled in by U-Boot */
218c06cf7daSStefan Roese				interrupt-parent = <&UIC1>;
219c06cf7daSStefan Roese				interrupts = <1d 4>;
220c06cf7daSStefan Roese			};
221c06cf7daSStefan Roese
222c06cf7daSStefan Roese			UART3: serial@ef600600 {
223c06cf7daSStefan Roese				device_type = "serial";
224c06cf7daSStefan Roese				compatible = "ns16550";
225c06cf7daSStefan Roese				reg = <ef600600 8>;
226c06cf7daSStefan Roese				virtual-reg = <ef600600>;
227c06cf7daSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
228c06cf7daSStefan Roese				current-speed = <0>; /* Filled in by U-Boot */
229c06cf7daSStefan Roese				interrupt-parent = <&UIC1>;
230c06cf7daSStefan Roese				interrupts = <1e 4>;
231c06cf7daSStefan Roese			};
232c06cf7daSStefan Roese
233c06cf7daSStefan Roese			IIC0: i2c@ef600700 {
234c06cf7daSStefan Roese				compatible = "ibm,iic-460gt", "ibm,iic";
235c06cf7daSStefan Roese				reg = <ef600700 14>;
236c06cf7daSStefan Roese				interrupt-parent = <&UIC0>;
237c06cf7daSStefan Roese				interrupts = <2 4>;
238c06cf7daSStefan Roese			};
239c06cf7daSStefan Roese
240c06cf7daSStefan Roese			IIC1: i2c@ef600800 {
241c06cf7daSStefan Roese				compatible = "ibm,iic-460gt", "ibm,iic";
242c06cf7daSStefan Roese				reg = <ef600800 14>;
243c06cf7daSStefan Roese				interrupt-parent = <&UIC0>;
244c06cf7daSStefan Roese				interrupts = <3 4>;
245c06cf7daSStefan Roese			};
246c06cf7daSStefan Roese
247c06cf7daSStefan Roese			ZMII0: emac-zmii@ef600d00 {
248c06cf7daSStefan Roese				compatible = "ibm,zmii-460gt", "ibm,zmii";
249c06cf7daSStefan Roese				reg = <ef600d00 c>;
250c06cf7daSStefan Roese			};
251c06cf7daSStefan Roese
252c06cf7daSStefan Roese			RGMII0: emac-rgmii@ef601500 {
253c06cf7daSStefan Roese				compatible = "ibm,rgmii-460gt", "ibm,rgmii";
254c06cf7daSStefan Roese				reg = <ef601500 8>;
255c06cf7daSStefan Roese				has-mdio;
256c06cf7daSStefan Roese			};
257c06cf7daSStefan Roese
258c06cf7daSStefan Roese			RGMII1: emac-rgmii@ef601600 {
259c06cf7daSStefan Roese				compatible = "ibm,rgmii-460gt", "ibm,rgmii";
260c06cf7daSStefan Roese				reg = <ef601600 8>;
261c06cf7daSStefan Roese				has-mdio;
262c06cf7daSStefan Roese			};
263c06cf7daSStefan Roese
264c06cf7daSStefan Roese			TAH0: emac-tah@ef601350 {
265c06cf7daSStefan Roese				compatible = "ibm,tah-460gt", "ibm,tah";
266c06cf7daSStefan Roese				reg = <ef601350 30>;
267c06cf7daSStefan Roese			};
268c06cf7daSStefan Roese
269c06cf7daSStefan Roese			TAH1: emac-tah@ef601450 {
270c06cf7daSStefan Roese				compatible = "ibm,tah-460gt", "ibm,tah";
271c06cf7daSStefan Roese				reg = <ef601450 30>;
272c06cf7daSStefan Roese			};
273c06cf7daSStefan Roese
274c06cf7daSStefan Roese			EMAC0: ethernet@ef600e00 {
275c06cf7daSStefan Roese				device_type = "network";
276c06cf7daSStefan Roese				compatible = "ibm,emac-460gt", "ibm,emac4";
277c06cf7daSStefan Roese				interrupt-parent = <&EMAC0>;
278c06cf7daSStefan Roese				interrupts = <0 1>;
279c06cf7daSStefan Roese				#interrupt-cells = <1>;
280c06cf7daSStefan Roese				#address-cells = <0>;
281c06cf7daSStefan Roese				#size-cells = <0>;
282c06cf7daSStefan Roese				interrupt-map = </*Status*/ 0 &UIC2 10 4
283c06cf7daSStefan Roese						 /*Wake*/   1 &UIC2 14 4>;
284c06cf7daSStefan Roese				reg = <ef600e00 70>;
285c06cf7daSStefan Roese				local-mac-address = [000000000000]; /* Filled in by U-Boot */
286c06cf7daSStefan Roese				mal-device = <&MAL0>;
287c06cf7daSStefan Roese				mal-tx-channel = <0>;
288c06cf7daSStefan Roese				mal-rx-channel = <0>;
289c06cf7daSStefan Roese				cell-index = <0>;
290c06cf7daSStefan Roese				max-frame-size = <2328>;
291c06cf7daSStefan Roese				rx-fifo-size = <1000>;
292c06cf7daSStefan Roese				tx-fifo-size = <800>;
293c06cf7daSStefan Roese				phy-mode = "rgmii";
294c06cf7daSStefan Roese				phy-map = <00000000>;
295c06cf7daSStefan Roese				rgmii-device = <&RGMII0>;
296c06cf7daSStefan Roese				rgmii-channel = <0>;
297c06cf7daSStefan Roese				tah-device = <&TAH0>;
298c06cf7daSStefan Roese				tah-channel = <0>;
299c06cf7daSStefan Roese				has-inverted-stacr-oc;
300c06cf7daSStefan Roese				has-new-stacr-staopc;
301c06cf7daSStefan Roese			};
302c06cf7daSStefan Roese
303c06cf7daSStefan Roese			EMAC1: ethernet@ef600f00 {
304c06cf7daSStefan Roese				device_type = "network";
305c06cf7daSStefan Roese				compatible = "ibm,emac-460gt", "ibm,emac4";
306c06cf7daSStefan Roese				interrupt-parent = <&EMAC1>;
307c06cf7daSStefan Roese				interrupts = <0 1>;
308c06cf7daSStefan Roese				#interrupt-cells = <1>;
309c06cf7daSStefan Roese				#address-cells = <0>;
310c06cf7daSStefan Roese				#size-cells = <0>;
311c06cf7daSStefan Roese				interrupt-map = </*Status*/ 0 &UIC2 11 4
312c06cf7daSStefan Roese						 /*Wake*/   1 &UIC2 15 4>;
313c06cf7daSStefan Roese				reg = <ef600f00 70>;
314c06cf7daSStefan Roese				local-mac-address = [000000000000]; /* Filled in by U-Boot */
315c06cf7daSStefan Roese				mal-device = <&MAL0>;
316c06cf7daSStefan Roese				mal-tx-channel = <1>;
317c06cf7daSStefan Roese				mal-rx-channel = <8>;
318c06cf7daSStefan Roese				cell-index = <1>;
319c06cf7daSStefan Roese				max-frame-size = <2328>;
320c06cf7daSStefan Roese				rx-fifo-size = <1000>;
321c06cf7daSStefan Roese				tx-fifo-size = <800>;
322c06cf7daSStefan Roese				phy-mode = "rgmii";
323c06cf7daSStefan Roese				phy-map = <00000000>;
324c06cf7daSStefan Roese				rgmii-device = <&RGMII0>;
325c06cf7daSStefan Roese				rgmii-channel = <1>;
326c06cf7daSStefan Roese				tah-device = <&TAH1>;
327a6190a84SStefan Roese				tah-channel = <1>;
328c06cf7daSStefan Roese				has-inverted-stacr-oc;
329c06cf7daSStefan Roese				has-new-stacr-staopc;
330a6190a84SStefan Roese				mdio-device = <&EMAC0>;
331c06cf7daSStefan Roese			};
332c06cf7daSStefan Roese
333c06cf7daSStefan Roese			EMAC2: ethernet@ef601100 {
334c06cf7daSStefan Roese				device_type = "network";
335c06cf7daSStefan Roese				compatible = "ibm,emac-460gt", "ibm,emac4";
336c06cf7daSStefan Roese				interrupt-parent = <&EMAC2>;
337c06cf7daSStefan Roese				interrupts = <0 1>;
338c06cf7daSStefan Roese				#interrupt-cells = <1>;
339c06cf7daSStefan Roese				#address-cells = <0>;
340c06cf7daSStefan Roese				#size-cells = <0>;
341c06cf7daSStefan Roese				interrupt-map = </*Status*/ 0 &UIC2 12 4
342c06cf7daSStefan Roese						 /*Wake*/   1 &UIC2 16 4>;
343c06cf7daSStefan Roese				reg = <ef601100 70>;
344c06cf7daSStefan Roese				local-mac-address = [000000000000]; /* Filled in by U-Boot */
345c06cf7daSStefan Roese				mal-device = <&MAL0>;
346c06cf7daSStefan Roese				mal-tx-channel = <2>;
347c06cf7daSStefan Roese				mal-rx-channel = <10>;
348c06cf7daSStefan Roese				cell-index = <2>;
349c06cf7daSStefan Roese				max-frame-size = <2328>;
350c06cf7daSStefan Roese				rx-fifo-size = <1000>;
351c06cf7daSStefan Roese				tx-fifo-size = <800>;
352c06cf7daSStefan Roese				phy-mode = "rgmii";
353c06cf7daSStefan Roese				phy-map = <00000000>;
354c06cf7daSStefan Roese				rgmii-device = <&RGMII1>;
355c06cf7daSStefan Roese				rgmii-channel = <0>;
356c06cf7daSStefan Roese				has-inverted-stacr-oc;
357c06cf7daSStefan Roese				has-new-stacr-staopc;
358a6190a84SStefan Roese				mdio-device = <&EMAC0>;
359c06cf7daSStefan Roese			};
360c06cf7daSStefan Roese
361c06cf7daSStefan Roese			EMAC3: ethernet@ef601200 {
362c06cf7daSStefan Roese				device_type = "network";
363c06cf7daSStefan Roese				compatible = "ibm,emac-460gt", "ibm,emac4";
364c06cf7daSStefan Roese				interrupt-parent = <&EMAC3>;
365c06cf7daSStefan Roese				interrupts = <0 1>;
366c06cf7daSStefan Roese				#interrupt-cells = <1>;
367c06cf7daSStefan Roese				#address-cells = <0>;
368c06cf7daSStefan Roese				#size-cells = <0>;
369c06cf7daSStefan Roese				interrupt-map = </*Status*/ 0 &UIC2 13 4
370c06cf7daSStefan Roese						 /*Wake*/   1 &UIC2 17 4>;
371c06cf7daSStefan Roese				reg = <ef601200 70>;
372c06cf7daSStefan Roese				local-mac-address = [000000000000]; /* Filled in by U-Boot */
373c06cf7daSStefan Roese				mal-device = <&MAL0>;
374c06cf7daSStefan Roese				mal-tx-channel = <3>;
375c06cf7daSStefan Roese				mal-rx-channel = <18>;
376c06cf7daSStefan Roese				cell-index = <3>;
377c06cf7daSStefan Roese				max-frame-size = <2328>;
378c06cf7daSStefan Roese				rx-fifo-size = <1000>;
379c06cf7daSStefan Roese				tx-fifo-size = <800>;
380c06cf7daSStefan Roese				phy-mode = "rgmii";
381c06cf7daSStefan Roese				phy-map = <00000000>;
382c06cf7daSStefan Roese				rgmii-device = <&RGMII1>;
383c06cf7daSStefan Roese				rgmii-channel = <1>;
384c06cf7daSStefan Roese				has-inverted-stacr-oc;
385c06cf7daSStefan Roese				has-new-stacr-staopc;
386a6190a84SStefan Roese				mdio-device = <&EMAC0>;
387c06cf7daSStefan Roese			};
388c06cf7daSStefan Roese		};
389c06cf7daSStefan Roese
390c06cf7daSStefan Roese		PCIX0: pci@c0ec00000 {
391c06cf7daSStefan Roese			device_type = "pci";
392c06cf7daSStefan Roese			#interrupt-cells = <1>;
393c06cf7daSStefan Roese			#size-cells = <2>;
394c06cf7daSStefan Roese			#address-cells = <3>;
395c06cf7daSStefan Roese			compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
396c06cf7daSStefan Roese			primary;
397c06cf7daSStefan Roese			large-inbound-windows;
398c06cf7daSStefan Roese			enable-msi-hole;
399c06cf7daSStefan Roese			reg = <c 0ec00000   8	/* Config space access */
400c06cf7daSStefan Roese			       0 0 0		/* no IACK cycles */
401c06cf7daSStefan Roese			       c 0ed00000   4   /* Special cycles */
402c06cf7daSStefan Roese			       c 0ec80000 100	/* Internal registers */
403c06cf7daSStefan Roese			       c 0ec80100  fc>;	/* Internal messaging registers */
404c06cf7daSStefan Roese
405c06cf7daSStefan Roese			/* Outbound ranges, one memory and one IO,
406c06cf7daSStefan Roese			 * later cannot be changed
407c06cf7daSStefan Roese			 */
408c06cf7daSStefan Roese			ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
409c06cf7daSStefan Roese				  01000000 0 00000000 0000000c 08000000 0 00010000>;
410c06cf7daSStefan Roese
411c06cf7daSStefan Roese			/* Inbound 2GB range starting at 0 */
412c06cf7daSStefan Roese			dma-ranges = <42000000 0 0 0 0 0 80000000>;
413c06cf7daSStefan Roese
414c06cf7daSStefan Roese			/* This drives busses 0 to 0x3f */
415c06cf7daSStefan Roese			bus-range = <0 3f>;
416c06cf7daSStefan Roese
417c06cf7daSStefan Roese			/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
418c06cf7daSStefan Roese			interrupt-map-mask = <0000 0 0 0>;
419c06cf7daSStefan Roese			interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
420c06cf7daSStefan Roese		};
421c06cf7daSStefan Roese
422c06cf7daSStefan Roese		PCIE0: pciex@d00000000 {
423c06cf7daSStefan Roese			device_type = "pci";
424c06cf7daSStefan Roese			#interrupt-cells = <1>;
425c06cf7daSStefan Roese			#size-cells = <2>;
426c06cf7daSStefan Roese			#address-cells = <3>;
427c06cf7daSStefan Roese			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
428c06cf7daSStefan Roese			primary;
429c06cf7daSStefan Roese			port = <0>; /* port number */
430c06cf7daSStefan Roese			reg = <d 00000000 20000000	/* Config space access */
431c06cf7daSStefan Roese			       c 08010000 00001000>;	/* Registers */
432c06cf7daSStefan Roese			dcr-reg = <100 020>;
433c06cf7daSStefan Roese			sdr-base = <300>;
434c06cf7daSStefan Roese
435c06cf7daSStefan Roese			/* Outbound ranges, one memory and one IO,
436c06cf7daSStefan Roese			 * later cannot be changed
437c06cf7daSStefan Roese			 */
438c06cf7daSStefan Roese			ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
439c06cf7daSStefan Roese				  01000000 0 00000000 0000000f 80000000 0 00010000>;
440c06cf7daSStefan Roese
441c06cf7daSStefan Roese			/* Inbound 2GB range starting at 0 */
442c06cf7daSStefan Roese			dma-ranges = <42000000 0 0 0 0 0 80000000>;
443c06cf7daSStefan Roese
444c06cf7daSStefan Roese			/* This drives busses 40 to 0x7f */
445c06cf7daSStefan Roese			bus-range = <40 7f>;
446c06cf7daSStefan Roese
447c06cf7daSStefan Roese			/* Legacy interrupts (note the weird polarity, the bridge seems
448c06cf7daSStefan Roese			 * to invert PCIe legacy interrupts).
449c06cf7daSStefan Roese			 * We are de-swizzling here because the numbers are actually for
450c06cf7daSStefan Roese			 * port of the root complex virtual P2P bridge. But I want
451c06cf7daSStefan Roese			 * to avoid putting a node for it in the tree, so the numbers
452c06cf7daSStefan Roese			 * below are basically de-swizzled numbers.
453c06cf7daSStefan Roese			 * The real slot is on idsel 0, so the swizzling is 1:1
454c06cf7daSStefan Roese			 */
455c06cf7daSStefan Roese			interrupt-map-mask = <0000 0 0 7>;
456c06cf7daSStefan Roese			interrupt-map = <
457c06cf7daSStefan Roese				0000 0 0 1 &UIC3 c 4 /* swizzled int A */
458c06cf7daSStefan Roese				0000 0 0 2 &UIC3 d 4 /* swizzled int B */
459c06cf7daSStefan Roese				0000 0 0 3 &UIC3 e 4 /* swizzled int C */
460c06cf7daSStefan Roese				0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
461c06cf7daSStefan Roese		};
462c06cf7daSStefan Roese
463c06cf7daSStefan Roese		PCIE1: pciex@d20000000 {
464c06cf7daSStefan Roese			device_type = "pci";
465c06cf7daSStefan Roese			#interrupt-cells = <1>;
466c06cf7daSStefan Roese			#size-cells = <2>;
467c06cf7daSStefan Roese			#address-cells = <3>;
468c06cf7daSStefan Roese			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
469c06cf7daSStefan Roese			primary;
470c06cf7daSStefan Roese			port = <1>; /* port number */
471c06cf7daSStefan Roese			reg = <d 20000000 20000000	/* Config space access */
472c06cf7daSStefan Roese			       c 08011000 00001000>;	/* Registers */
473c06cf7daSStefan Roese			dcr-reg = <120 020>;
474c06cf7daSStefan Roese			sdr-base = <340>;
475c06cf7daSStefan Roese
476c06cf7daSStefan Roese			/* Outbound ranges, one memory and one IO,
477c06cf7daSStefan Roese			 * later cannot be changed
478c06cf7daSStefan Roese			 */
479c06cf7daSStefan Roese			ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
480c06cf7daSStefan Roese				  01000000 0 00000000 0000000f 80010000 0 00010000>;
481c06cf7daSStefan Roese
482c06cf7daSStefan Roese			/* Inbound 2GB range starting at 0 */
483c06cf7daSStefan Roese			dma-ranges = <42000000 0 0 0 0 0 80000000>;
484c06cf7daSStefan Roese
485c06cf7daSStefan Roese			/* This drives busses 80 to 0xbf */
486c06cf7daSStefan Roese			bus-range = <80 bf>;
487c06cf7daSStefan Roese
488c06cf7daSStefan Roese			/* Legacy interrupts (note the weird polarity, the bridge seems
489c06cf7daSStefan Roese			 * to invert PCIe legacy interrupts).
490c06cf7daSStefan Roese			 * We are de-swizzling here because the numbers are actually for
491c06cf7daSStefan Roese			 * port of the root complex virtual P2P bridge. But I want
492c06cf7daSStefan Roese			 * to avoid putting a node for it in the tree, so the numbers
493c06cf7daSStefan Roese			 * below are basically de-swizzled numbers.
494c06cf7daSStefan Roese			 * The real slot is on idsel 0, so the swizzling is 1:1
495c06cf7daSStefan Roese			 */
496c06cf7daSStefan Roese			interrupt-map-mask = <0000 0 0 7>;
497c06cf7daSStefan Roese			interrupt-map = <
498c06cf7daSStefan Roese				0000 0 0 1 &UIC3 10 4 /* swizzled int A */
499c06cf7daSStefan Roese				0000 0 0 2 &UIC3 11 4 /* swizzled int B */
500c06cf7daSStefan Roese				0000 0 0 3 &UIC3 12 4 /* swizzled int C */
501c06cf7daSStefan Roese				0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
502c06cf7daSStefan Roese		};
503c06cf7daSStefan Roese	};
504c06cf7daSStefan Roese};
505