1/* 2 * Device Tree Source for FSP2 3 * 4 * Copyright 2010,2012 IBM Corp. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without 8 * any warranty of any kind, whether express or implied. 9 */ 10 11 12/dts-v1/; 13 14/ { 15 #address-cells = <2>; 16 #size-cells = <1>; 17 model = "ibm,fsp2"; 18 compatible = "ibm,fsp2"; 19 dcr-parent = <&{/cpus/cpu@0}>; 20 21 aliases { 22 ethernet0 = &EMAC0; 23 ethernet1 = &EMAC1; 24 serial0 = &UART0; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 device_type = "cpu"; 33 model = "PowerPC, 476FSP2"; 34 reg = <0x0>; 35 clock-frequency = <0>; /* Filled in by cuboot */ 36 timebase-frequency = <0>; /* Filled in by cuboot */ 37 i-cache-line-size = <32>; 38 d-cache-line-size = <32>; 39 d-cache-size = <32768>; 40 i-cache-size = <32768>; 41 dcr-controller; 42 dcr-access-method = "native"; 43 }; 44 }; 45 46 memory { 47 device_type = "memory"; 48 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by 49 cuboot */ 50 }; 51 52 clocks { 53 mmc_clk: mmc_clk { 54 compatible = "fixed-clock"; 55 clock-frequency = <50000000>; 56 clock-output-names = "mmc_clk"; 57 }; 58 }; 59 60 UIC0: uic0 { 61 #address-cells = <0>; 62 #size-cells = <0>; 63 #interrupt-cells = <2>; 64 compatible = "ibm,uic"; 65 interrupt-controller; 66 cell-index = <0>; 67 dcr-reg = <0x2c0 0x8>; 68 }; 69 70 /* "interrupts" field is <bit level bit level> 71 first pair is non-critical, second is critical */ 72 UIC1_0: uic1_0 { 73 #address-cells = <0>; 74 #size-cells = <0>; 75 #interrupt-cells = <2>; 76 77 compatible = "ibm,uic"; 78 interrupt-controller; 79 cell-index = <1>; 80 dcr-reg = <0x2c8 0x8>; 81 interrupt-parent = <&UIC0>; 82 interrupts = <21 0x4 4 0x84>; 83 }; 84 85 /* PSI and DMA */ 86 UIC1_1: uic1_1 { 87 #address-cells = <0>; 88 #size-cells = <0>; 89 #interrupt-cells = <2>; 90 91 compatible = "ibm,uic"; 92 interrupt-controller; 93 cell-index = <2>; 94 dcr-reg = <0x350 0x8>; 95 interrupt-parent = <&UIC0>; 96 interrupts = <22 0x4 5 0x84>; 97 }; 98 99 /* Ethernet and USB */ 100 UIC1_2: uic1_2 { 101 #address-cells = <0>; 102 #size-cells = <0>; 103 #interrupt-cells = <2>; 104 105 compatible = "ibm,uic"; 106 interrupt-controller; 107 cell-index = <3>; 108 dcr-reg = <0x358 0x8>; 109 interrupt-parent = <&UIC0>; 110 interrupts = <23 0x4 6 0x84>; 111 }; 112 113 /* PLB Errors */ 114 UIC1_3: uic1_3 { 115 #address-cells = <0>; 116 #size-cells = <0>; 117 #interrupt-cells = <2>; 118 119 compatible = "ibm,uic"; 120 interrupt-controller; 121 cell-index = <4>; 122 dcr-reg = <0x360 0x8>; 123 interrupt-parent = <&UIC0>; 124 interrupts = <24 0x4 7 0x84>; 125 }; 126 127 UIC1_4: uic1_4 { 128 #address-cells = <0>; 129 #size-cells = <0>; 130 #interrupt-cells = <2>; 131 132 compatible = "ibm,uic"; 133 interrupt-controller; 134 cell-index = <5>; 135 dcr-reg = <0x368 0x8>; 136 interrupt-parent = <&UIC0>; 137 interrupts = <25 0x4 8 0x84>; 138 }; 139 140 UIC1_5: uic1_5 { 141 #address-cells = <0>; 142 #size-cells = <0>; 143 #interrupt-cells = <2>; 144 145 compatible = "ibm,uic"; 146 interrupt-controller; 147 cell-index = <6>; 148 dcr-reg = <0x370 0x8>; 149 interrupt-parent = <&UIC0>; 150 interrupts = <26 0x4 9 0x84>; 151 }; 152 153 /* 2nd level UICs for FSI */ 154 UIC2_0: uic2_0 { 155 #address-cells = <0>; 156 #size-cells = <0>; 157 #interrupt-cells = <2>; 158 159 compatible = "ibm,uic"; 160 interrupt-controller; 161 cell-index = <7>; 162 dcr-reg = <0x2d0 0x8>; 163 interrupt-parent = <&UIC1_0>; 164 interrupts = <16 0x4 0 0x84>; 165 }; 166 167 UIC2_1: uic2_1 { 168 #address-cells = <0>; 169 #size-cells = <0>; 170 #interrupt-cells = <2>; 171 172 compatible = "ibm,uic"; 173 interrupt-controller; 174 cell-index = <8>; 175 dcr-reg = <0x2d8 0x8>; 176 interrupt-parent = <&UIC1_0>; 177 interrupts = <17 0x4 1 0x84>; 178 }; 179 180 UIC2_2: uic2_2 { 181 #address-cells = <0>; 182 #size-cells = <0>; 183 #interrupt-cells = <2>; 184 185 compatible = "ibm,uic"; 186 interrupt-controller; 187 cell-index = <9>; 188 dcr-reg = <0x2e0 0x8>; 189 interrupt-parent = <&UIC1_0>; 190 interrupts = <18 0x4 2 0x84>; 191 }; 192 193 UIC2_3: uic2_3 { 194 #address-cells = <0>; 195 #size-cells = <0>; 196 #interrupt-cells = <2>; 197 198 compatible = "ibm,uic"; 199 interrupt-controller; 200 cell-index = <10>; 201 dcr-reg = <0x2e8 0x8>; 202 interrupt-parent = <&UIC1_0>; 203 interrupts = <19 0x4 3 0x84>; 204 }; 205 206 UIC2_4: uic2_4 { 207 #address-cells = <0>; 208 #size-cells = <0>; 209 #interrupt-cells = <2>; 210 211 compatible = "ibm,uic"; 212 interrupt-controller; 213 cell-index = <11>; 214 dcr-reg = <0x2f0 0x8>; 215 interrupt-parent = <&UIC1_0>; 216 interrupts = <20 0x4 4 0x84>; 217 }; 218 219 UIC2_5: uic2_5 { 220 #address-cells = <0>; 221 #size-cells = <0>; 222 #interrupt-cells = <2>; 223 224 compatible = "ibm,uic"; 225 interrupt-controller; 226 cell-index = <12>; 227 dcr-reg = <0x2f8 0x8>; 228 interrupt-parent = <&UIC1_0>; 229 interrupts = <21 0x4 5 0x84>; 230 }; 231 232 UIC2_6: uic2_6 { 233 #address-cells = <0>; 234 #size-cells = <0>; 235 #interrupt-cells = <2>; 236 237 compatible = "ibm,uic"; 238 interrupt-controller; 239 cell-index = <13>; 240 dcr-reg = <0x300 0x8>; 241 interrupt-parent = <&UIC1_0>; 242 interrupts = <22 0x4 6 0x84>; 243 }; 244 245 UIC2_7: uic2_7 { 246 #address-cells = <0>; 247 #size-cells = <0>; 248 #interrupt-cells = <2>; 249 250 compatible = "ibm,uic"; 251 interrupt-controller; 252 cell-index = <14>; 253 dcr-reg = <0x308 0x8>; 254 interrupt-parent = <&UIC1_0>; 255 interrupts = <23 0x4 7 0x84>; 256 }; 257 258 UIC2_8: uic2_8 { 259 #address-cells = <0>; 260 #size-cells = <0>; 261 #interrupt-cells = <2>; 262 263 compatible = "ibm,uic"; 264 interrupt-controller; 265 cell-index = <15>; 266 dcr-reg = <0x310 0x8>; 267 interrupt-parent = <&UIC1_0>; 268 interrupts = <24 0x4 8 0x84>; 269 }; 270 271 UIC2_9: uic2_9 { 272 #address-cells = <0>; 273 #size-cells = <0>; 274 #interrupt-cells = <2>; 275 276 compatible = "ibm,uic"; 277 interrupt-controller; 278 cell-index = <16>; 279 dcr-reg = <0x318 0x8>; 280 interrupt-parent = <&UIC1_0>; 281 interrupts = <25 0x4 9 0x84>; 282 }; 283 284 UIC2_10: uic2_10 { 285 #address-cells = <0>; 286 #size-cells = <0>; 287 #interrupt-cells = <2>; 288 289 compatible = "ibm,uic"; 290 interrupt-controller; 291 cell-index = <17>; 292 dcr-reg = <0x320 0x8>; 293 interrupt-parent = <&UIC1_0>; 294 interrupts = <26 0x4 10 0x84>; 295 }; 296 297 UIC2_11: uic2_11 { 298 #address-cells = <0>; 299 #size-cells = <0>; 300 #interrupt-cells = <2>; 301 302 compatible = "ibm,uic"; 303 interrupt-controller; 304 cell-index = <18>; 305 dcr-reg = <0x328 0x8>; 306 interrupt-parent = <&UIC1_0>; 307 interrupts = <27 0x4 11 0x84>; 308 }; 309 310 UIC2_12: uic2_12 { 311 #address-cells = <0>; 312 #size-cells = <0>; 313 #interrupt-cells = <2>; 314 315 compatible = "ibm,uic"; 316 interrupt-controller; 317 cell-index = <19>; 318 dcr-reg = <0x330 0x8>; 319 interrupt-parent = <&UIC1_0>; 320 interrupts = <28 0x4 12 0x84>; 321 }; 322 323 UIC2_13: uic2_13 { 324 #address-cells = <0>; 325 #size-cells = <0>; 326 #interrupt-cells = <2>; 327 328 compatible = "ibm,uic"; 329 interrupt-controller; 330 cell-index = <20>; 331 dcr-reg = <0x338 0x8>; 332 interrupt-parent = <&UIC1_0>; 333 interrupts = <29 0x4 13 0x84>; 334 }; 335 336 UIC2_14: uic2_14 { 337 #address-cells = <0>; 338 #size-cells = <0>; 339 #interrupt-cells = <2>; 340 341 compatible = "ibm,uic"; 342 interrupt-controller; 343 cell-index = <21>; 344 dcr-reg = <0x340 0x8>; 345 interrupt-parent = <&UIC1_0>; 346 interrupts = <30 0x4 14 0x84>; 347 }; 348 349 UIC2_15: uic2_15 { 350 #address-cells = <0>; 351 #size-cells = <0>; 352 #interrupt-cells = <2>; 353 354 compatible = "ibm,uic"; 355 interrupt-controller; 356 cell-index = <22>; 357 dcr-reg = <0x348 0x8>; 358 interrupt-parent = <&UIC1_0>; 359 interrupts = <31 0x4 15 0x84>; 360 }; 361 362 mmc0: sdhci@020c0000 { 363 compatible = "st,sdhci-stih407", "st,sdhci"; 364 status = "disabled"; 365 reg = <0x020c0000 0x20000>; 366 reg-names = "mmc"; 367 interrupt-parent = <&UIC1_3>; 368 interrupts = <21 0x4 22 0x4>; 369 interrupt-names = "mmcirq"; 370 pinctrl-names = "default"; 371 pinctrl-0 = <>; 372 clock-names = "mmc"; 373 clocks = <&mmc_clk>; 374 }; 375 376 plb6 { 377 compatible = "ibm,plb6"; 378 #address-cells = <2>; 379 #size-cells = <1>; 380 ranges; 381 382 MCW0: memory-controller-wrapper { 383 compatible = "ibm,cw-476fsp2"; 384 dcr-reg = <0x11111800 0x40>; 385 }; 386 387 MCIF0: memory-controller { 388 compatible = "ibm,sdram-476fsp2", "ibm,sdram-4xx-ddr3"; 389 dcr-reg = <0x11120000 0x10000>; 390 mcer-device = <&MCW0>; 391 interrupt-parent = <&UIC0>; 392 interrupts = <10 0x84 /* ECC UE */ 393 11 0x84>; /* ECC CE */ 394 }; 395 }; 396 397 plb4 { 398 compatible = "ibm,plb4"; 399 #address-cells = <1>; 400 #size-cells = <1>; 401 ranges = <0x00000000 0x00000010 0x00000000 0x80000000 402 0x80000000 0x00000010 0x80000000 0x80000000>; 403 clock-frequency = <333333334>; 404 405 plb6-system-hung-irq { 406 compatible = "ibm,bus-error-irq"; 407 #interrupt-cells = <2>; 408 interrupt-parent = <&UIC0>; 409 interrupts = <0 0x84>; 410 }; 411 412 l2-error-irq { 413 compatible = "ibm,bus-error-irq"; 414 #interrupt-cells = <2>; 415 interrupt-parent = <&UIC0>; 416 interrupts = <20 0x84>; 417 }; 418 419 plb6-plb4-irq { 420 compatible = "ibm,bus-error-irq"; 421 #interrupt-cells = <2>; 422 interrupt-parent = <&UIC0>; 423 interrupts = <1 0x84>; 424 }; 425 426 plb4-ahb-irq { 427 compatible = "ibm,bus-error-irq"; 428 #interrupt-cells = <2>; 429 interrupt-parent = <&UIC1_3>; 430 interrupts = <20 0x84>; 431 }; 432 433 opbd-error-irq { 434 compatible = "ibm,opbd-error-irq"; 435 #interrupt-cells = <2>; 436 interrupt-parent = <&UIC1_4>; 437 interrupts = <5 0x84>; 438 }; 439 440 cmu-error-irq { 441 compatible = "ibm,cmu-error-irq"; 442 #interrupt-cells = <2>; 443 interrupt-parent = <&UIC0>; 444 interrupts = <28 0x84>; 445 }; 446 447 conf-error-irq { 448 compatible = "ibm,conf-error-irq"; 449 #interrupt-cells = <2>; 450 interrupt-parent = <&UIC1_4>; 451 interrupts = <11 0x84>; 452 }; 453 454 mc-ue-irq { 455 compatible = "ibm,mc-ue-irq"; 456 #interrupt-cells = <2>; 457 interrupt-parent = <&UIC0>; 458 interrupts = <10 0x84>; 459 }; 460 461 reset-warning-irq { 462 compatible = "ibm,reset-warning-irq"; 463 #interrupt-cells = <2>; 464 interrupt-parent = <&UIC0>; 465 interrupts = <17 0x84>; 466 }; 467 468 MAL0: mcmal0 { 469 #interrupt-cells = <1>; 470 #address-cells = <0>; 471 #size-cells = <0>; 472 compatible = "ibm,mcmal"; 473 dcr-reg = <0x80 0x80>; 474 num-tx-chans = <1>; 475 num-rx-chans = <1>; 476 interrupt-parent = <&MAL0>; 477 interrupts = <0 1 2 3 4>; 478 /* index interrupt-parent interrupt# type */ 479 interrupt-map = </*TXEOB*/ 0 &UIC1_2 4 0x4 480 /*RXEOB*/ 1 &UIC1_2 3 0x4 481 /*SERR*/ 2 &UIC1_2 7 0x4 482 /*TXDE*/ 3 &UIC1_2 6 0x4 483 /*RXDE*/ 4 &UIC1_2 5 0x4>; 484 }; 485 486 MAL1: mcmal1 { 487 #interrupt-cells = <1>; 488 #address-cells = <0>; 489 #size-cells = <0>; 490 compatible = "ibm,mcmal"; 491 dcr-reg = <0x100 0x80>; 492 num-tx-chans = <1>; 493 num-rx-chans = <1>; 494 interrupt-parent = <&MAL1>; 495 interrupts = <0 1 2 3 4>; 496 /* index interrupt-parent interrupt# type */ 497 interrupt-map = </*TXEOB*/ 0 &UIC1_2 12 0x4 498 /*RXEOB*/ 1 &UIC1_2 11 0x4 499 /*SERR*/ 2 &UIC1_2 15 0x4 500 /*TXDE*/ 3 &UIC1_2 14 0x4 501 /*RXDE*/ 4 &UIC1_2 13 0x4>; 502 }; 503 504 opb { 505 compatible = "ibm,opb"; 506 #address-cells = <1>; 507 #size-cells = <1>; 508 ranges; // pass-thru to parent bus 509 clock-frequency = <83333334>; 510 511 EMAC0: ethernet@b0000000 { 512 linux,network-index = <0>; 513 device_type = "network"; 514 compatible = "ibm,emac4sync"; 515 has-inverted-stacr-oc; 516 interrupt-parent = <&UIC1_2>; 517 interrupts = <1 0x4 0 0x4>; 518 reg = <0xb0000000 0x100>; 519 local-mac-address = [000000000000]; /* Filled in by 520 cuboot */ 521 mal-device = <&MAL0>; 522 mal-tx-channel = <0>; 523 mal-rx-channel = <0>; 524 cell-index = <0>; 525 max-frame-size = <1500>; 526 rx-fifo-size = <4096>; 527 tx-fifo-size = <4096>; 528 rx-fifo-size-gige = <16384>; 529 tx-fifo-size-gige = <8192>; 530 phy-address = <1>; 531 phy-mode = "rgmii"; 532 phy-map = <00000003>; 533 rgmii-device = <&RGMII>; 534 rgmii-channel = <0>; 535 }; 536 537 EMAC1: ethernet@b0000100 { 538 linux,network-index = <1>; 539 device_type = "network"; 540 compatible = "ibm,emac4sync"; 541 has-inverted-stacr-oc; 542 interrupt-parent = <&UIC1_2>; 543 interrupts = <9 0x4 8 0x4>; 544 reg = <0xb0000100 0x100>; 545 local-mac-address = [000000000000]; /* Filled in by 546 cuboot */ 547 mal-device = <&MAL1>; 548 mal-tx-channel = <0>; 549 mal-rx-channel = <0>; 550 cell-index = <1>; 551 max-frame-size = <1500>; 552 rx-fifo-size = <4096>; 553 tx-fifo-size = <4096>; 554 rx-fifo-size-gige = <16384>; 555 tx-fifo-size-gige = <8192>; 556 phy-address = <2>; 557 phy-mode = "rgmii"; 558 phy-map = <00000003>; 559 rgmii-device = <&RGMII>; 560 rgmii-channel = <1>; 561 }; 562 563 RGMII: rgmii@b0000600 { 564 compatible = "ibm,rgmii"; 565 has-mdio; 566 reg = <0xb0000600 0x8>; 567 }; 568 569 UART0: serial@b0020000 { 570 device_type = "serial"; 571 compatible = "ns16550"; 572 reg = <0xb0020000 0x8>; 573 virtual-reg = <0xb0020000>; 574 clock-frequency = <20833333>; 575 current-speed = <115200>; 576 interrupt-parent = <&UIC0>; 577 interrupts = <31 0x4>; 578 }; 579 }; 580 581 OHCI1: ohci@02040000 { 582 compatible = "ohci-le"; 583 reg = <0x02040000 0xa0>; 584 interrupt-parent = <&UIC1_3>; 585 interrupts = <28 0x8 29 0x8>; 586 }; 587 588 OHCI2: ohci@02080000 { 589 compatible = "ohci-le"; 590 reg = <0x02080000 0xa0>; 591 interrupt-parent = <&UIC1_3>; 592 interrupts = <30 0x8 31 0x8>; 593 }; 594 595 EHCI: ehci@02000000 { 596 compatible = "usb-ehci"; 597 reg = <0x02000000 0xa4>; 598 interrupt-parent = <&UIC1_3>; 599 interrupts = <23 0x4>; 600 }; 601 602 }; 603 604 chosen { 605 linux,stdout-path = "/plb/opb/serial@b0020000"; 606 bootargs = "console=ttyS0,115200 rw log_buf_len=32768 debug"; 607 }; 608}; 609