1/*
2 * T4240 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e6500_power_isa.dtsi"
38
39/ {
40	compatible = "fsl,T4240";
41	#address-cells = <2>;
42	#size-cells = <2>;
43	interrupt-parent = <&mpic>;
44
45	aliases {
46		ccsr = &soc;
47		dcsr = &dcsr;
48
49		serial0 = &serial0;
50		serial1 = &serial1;
51		serial2 = &serial2;
52		serial3 = &serial3;
53		crypto = &crypto;
54		pci0 = &pci0;
55		pci1 = &pci1;
56		pci2 = &pci2;
57		pci3 = &pci3;
58		dma0 = &dma0;
59		dma1 = &dma1;
60		sdhc = &sdhc;
61	};
62
63	cpus {
64		#address-cells = <1>;
65		#size-cells = <0>;
66
67		cpu0: PowerPC,e6500@0 {
68			device_type = "cpu";
69			reg = <0 1>;
70			clocks = <&mux0>;
71			next-level-cache = <&L2_1>;
72		};
73		cpu1: PowerPC,e6500@2 {
74			device_type = "cpu";
75			reg = <2 3>;
76			clocks = <&mux0>;
77			next-level-cache = <&L2_1>;
78		};
79		cpu2: PowerPC,e6500@4 {
80			device_type = "cpu";
81			reg = <4 5>;
82			clocks = <&mux0>;
83			next-level-cache = <&L2_1>;
84		};
85		cpu3: PowerPC,e6500@6 {
86			device_type = "cpu";
87			reg = <6 7>;
88			clocks = <&mux0>;
89			next-level-cache = <&L2_1>;
90		};
91		cpu4: PowerPC,e6500@8 {
92			device_type = "cpu";
93			reg = <8 9>;
94			clocks = <&mux1>;
95			next-level-cache = <&L2_2>;
96		};
97		cpu5: PowerPC,e6500@10 {
98			device_type = "cpu";
99			reg = <10 11>;
100			clocks = <&mux1>;
101			next-level-cache = <&L2_2>;
102		};
103		cpu6: PowerPC,e6500@12 {
104			device_type = "cpu";
105			reg = <12 13>;
106			clocks = <&mux1>;
107			next-level-cache = <&L2_2>;
108		};
109		cpu7: PowerPC,e6500@14 {
110			device_type = "cpu";
111			reg = <14 15>;
112			clocks = <&mux1>;
113			next-level-cache = <&L2_2>;
114		};
115		cpu8: PowerPC,e6500@16 {
116			device_type = "cpu";
117			reg = <16 17>;
118			clocks = <&mux2>;
119			next-level-cache = <&L2_3>;
120		};
121		cpu9: PowerPC,e6500@18 {
122			device_type = "cpu";
123			reg = <18 19>;
124			clocks = <&mux2>;
125			next-level-cache = <&L2_3>;
126		};
127		cpu10: PowerPC,e6500@20 {
128			device_type = "cpu";
129			reg = <20 21>;
130			clocks = <&mux2>;
131			next-level-cache = <&L2_3>;
132		};
133		cpu11: PowerPC,e6500@22 {
134			device_type = "cpu";
135			reg = <22 23>;
136			clocks = <&mux2>;
137			next-level-cache = <&L2_3>;
138		};
139	};
140};
141