1/*
2 * T2080/T2081 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *	 notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *	 notice, this list of conditions and the following disclaimer in the
12 *	 documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *	 names of its contributors may be used to endorse or promote products
15 *	 derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e6500_power_isa.dtsi"
38
39/ {
40	#address-cells = <2>;
41	#size-cells = <2>;
42	interrupt-parent = <&mpic>;
43
44	aliases {
45		ccsr = &soc;
46		dcsr = &dcsr;
47
48		serial0 = &serial0;
49		serial1 = &serial1;
50		serial2 = &serial2;
51		serial3 = &serial3;
52
53		crypto = &crypto;
54		pci0 = &pci0;
55		pci1 = &pci1;
56		pci2 = &pci2;
57		pci3 = &pci3;
58		usb0 = &usb0;
59		usb1 = &usb1;
60		dma0 = &dma0;
61		dma1 = &dma1;
62		dma2 = &dma2;
63		sdhc = &sdhc;
64	};
65
66	cpus {
67		#address-cells = <1>;
68		#size-cells = <0>;
69
70		cpu0: PowerPC,e6500@0 {
71			device_type = "cpu";
72			reg = <0 1>;
73			clocks = <&mux0>;
74			next-level-cache = <&L2_1>;
75			fsl,portid-mapping = <0x80000000>;
76		};
77		cpu1: PowerPC,e6500@2 {
78			device_type = "cpu";
79			reg = <2 3>;
80			clocks = <&mux0>;
81			next-level-cache = <&L2_1>;
82			fsl,portid-mapping = <0x80000000>;
83		};
84		cpu2: PowerPC,e6500@4 {
85			device_type = "cpu";
86			reg = <4 5>;
87			clocks = <&mux0>;
88			next-level-cache = <&L2_1>;
89			fsl,portid-mapping = <0x80000000>;
90		};
91		cpu3: PowerPC,e6500@6 {
92			device_type = "cpu";
93			reg = <6 7>;
94			clocks = <&mux0>;
95			next-level-cache = <&L2_1>;
96			fsl,portid-mapping = <0x80000000>;
97		};
98	};
99};
100