1/*
2 * T2081 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *	 notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *	 notice, this list of conditions and the following disclaimer in the
12 *	 documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *	 names of its contributors may be used to endorse or promote products
15 *	 derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36	#address-cells = <2>;
37	#size-cells = <1>;
38	compatible = "fsl,ifc", "simple-bus";
39	interrupts = <25 2 0 0>;
40};
41
42/* controller at 0x240000 */
43&pci0 {
44	compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
45	device_type = "pci";
46	#size-cells = <2>;
47	#address-cells = <3>;
48	bus-range = <0x0 0xff>;
49	interrupts = <20 2 0 0>;
50	fsl,iommu-parent = <&pamu0>;
51	pcie@0 {
52		reg = <0 0 0 0 0>;
53		#interrupt-cells = <1>;
54		#size-cells = <2>;
55		#address-cells = <3>;
56		device_type = "pci";
57		interrupts = <20 2 0 0>;
58		interrupt-map-mask = <0xf800 0 0 7>;
59		interrupt-map = <
60			/* IDSEL 0x0 */
61			0000 0 0 1 &mpic 40 1 0 0
62			0000 0 0 2 &mpic 1 1 0 0
63			0000 0 0 3 &mpic 2 1 0 0
64			0000 0 0 4 &mpic 3 1 0 0
65		>;
66	};
67};
68
69/* controller at 0x250000 */
70&pci1 {
71	compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
72	device_type = "pci";
73	#size-cells = <2>;
74	#address-cells = <3>;
75	bus-range = <0 0xff>;
76	interrupts = <21 2 0 0>;
77	fsl,iommu-parent = <&pamu0>;
78	pcie@0 {
79		reg = <0 0 0 0 0>;
80		#interrupt-cells = <1>;
81		#size-cells = <2>;
82		#address-cells = <3>;
83		device_type = "pci";
84		interrupts = <21 2 0 0>;
85		interrupt-map-mask = <0xf800 0 0 7>;
86		interrupt-map = <
87			/* IDSEL 0x0 */
88			0000 0 0 1 &mpic 41 1 0 0
89			0000 0 0 2 &mpic 5 1 0 0
90			0000 0 0 3 &mpic 6 1 0 0
91			0000 0 0 4 &mpic 7 1 0 0
92		>;
93	};
94};
95
96/* controller at 0x260000 */
97&pci2 {
98	compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
99	device_type = "pci";
100	#size-cells = <2>;
101	#address-cells = <3>;
102	bus-range = <0x0 0xff>;
103	interrupts = <22 2 0 0>;
104	fsl,iommu-parent = <&pamu0>;
105	pcie@0 {
106		reg = <0 0 0 0 0>;
107		#interrupt-cells = <1>;
108		#size-cells = <2>;
109		#address-cells = <3>;
110		device_type = "pci";
111		interrupts = <22 2 0 0>;
112		interrupt-map-mask = <0xf800 0 0 7>;
113		interrupt-map = <
114			/* IDSEL 0x0 */
115			0000 0 0 1 &mpic 42 1 0 0
116			0000 0 0 2 &mpic 9 1 0 0
117			0000 0 0 3 &mpic 10 1 0 0
118			0000 0 0 4 &mpic 11 1 0 0
119		>;
120	};
121};
122
123/* controller at 0x270000 */
124&pci3 {
125	compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
126	device_type = "pci";
127	#size-cells = <2>;
128	#address-cells = <3>;
129	bus-range = <0x0 0xff>;
130	interrupts = <23 2 0 0>;
131	fsl,iommu-parent = <&pamu0>;
132	pcie@0 {
133		reg = <0 0 0 0 0>;
134		#interrupt-cells = <1>;
135		#size-cells = <2>;
136		#address-cells = <3>;
137		device_type = "pci";
138		interrupts = <23 2 0 0>;
139		interrupt-map-mask = <0xf800 0 0 7>;
140		interrupt-map = <
141			/* IDSEL 0x0 */
142			0000 0 0 1 &mpic 43 1 0 0
143			0000 0 0 2 &mpic 0 1 0 0
144			0000 0 0 3 &mpic 4 1 0 0
145			0000 0 0 4 &mpic 8 1 0 0
146		>;
147	};
148};
149
150&dcsr {
151	#address-cells = <1>;
152	#size-cells = <1>;
153	compatible = "fsl,dcsr", "simple-bus";
154
155	dcsr-epu@0 {
156		compatible = "fsl,t2080-dcsr-epu", "fsl,dcsr-epu";
157		interrupts = <52 2 0 0
158			      84 2 0 0
159			      85 2 0 0
160			      94 2 0 0
161			      95 2 0 0>;
162		reg = <0x0 0x1000>;
163	};
164	dcsr-npc {
165		compatible = "fsl,t2080-dcsr-cnpc", "fsl,dcsr-cnpc";
166		reg = <0x1000 0x1000 0x1002000 0x10000>;
167	};
168	dcsr-nxc@2000 {
169		compatible = "fsl,dcsr-nxc";
170		reg = <0x2000 0x1000>;
171	};
172	dcsr-corenet {
173		compatible = "fsl,dcsr-corenet";
174		reg = <0x8000 0x1000 0x1A000 0x1000>;
175	};
176	dcsr-ocn@11000 {
177		compatible = "fsl,t2080-dcsr-ocn", "fsl,dcsr-ocn";
178		reg = <0x11000 0x1000>;
179	};
180	dcsr-ddr@12000 {
181		compatible = "fsl,dcsr-ddr";
182		dev-handle = <&ddr1>;
183		reg = <0x12000 0x1000>;
184	};
185	dcsr-nal@18000 {
186		compatible = "fsl,t2080-dcsr-nal", "fsl,dcsr-nal";
187		reg = <0x18000 0x1000>;
188	};
189	dcsr-rcpm@22000 {
190		compatible = "fsl,t2080-dcsr-rcpm", "fsl,dcsr-rcpm";
191		reg = <0x22000 0x1000>;
192	};
193	dcsr-snpc@30000 {
194		compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
195		reg = <0x30000 0x1000 0x1022000 0x10000>;
196	};
197	dcsr-snpc@31000 {
198		compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
199		reg = <0x31000 0x1000 0x1042000 0x10000>;
200	};
201	dcsr-snpc@32000 {
202		compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
203		reg = <0x32000 0x1000 0x1062000 0x10000>;
204	};
205	dcsr-cpu-sb-proxy@100000 {
206		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
207		cpu-handle = <&cpu0>;
208		reg = <0x100000 0x1000 0x101000 0x1000>;
209	};
210	dcsr-cpu-sb-proxy@108000 {
211		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
212		cpu-handle = <&cpu1>;
213		reg = <0x108000 0x1000 0x109000 0x1000>;
214	};
215	dcsr-cpu-sb-proxy@110000 {
216		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
217		cpu-handle = <&cpu2>;
218		reg = <0x110000 0x1000 0x111000 0x1000>;
219	};
220	dcsr-cpu-sb-proxy@118000 {
221		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
222		cpu-handle = <&cpu3>;
223		reg = <0x118000 0x1000 0x119000 0x1000>;
224	};
225};
226
227&soc {
228	#address-cells = <1>;
229	#size-cells = <1>;
230	device_type = "soc";
231	compatible = "simple-bus";
232
233	soc-sram-error {
234		compatible = "fsl,soc-sram-error";
235		interrupts = <16 2 1 29>;
236	};
237
238	corenet-law@0 {
239		compatible = "fsl,corenet-law";
240		reg = <0x0 0x1000>;
241		fsl,num-laws = <32>;
242	};
243
244	ddr1: memory-controller@8000 {
245		compatible = "fsl,qoriq-memory-controller-v4.7",
246				"fsl,qoriq-memory-controller";
247		reg = <0x8000 0x1000>;
248		interrupts = <16 2 1 23>;
249	};
250
251	cpc: l3-cache-controller@10000 {
252		compatible = "fsl,t2080-l3-cache-controller", "cache";
253		reg = <0x10000 0x1000
254		       0x11000 0x1000
255		       0x12000 0x1000>;
256		interrupts = <16 2 1 27
257			      16 2 1 26
258			      16 2 1 25>;
259	};
260
261	corenet-cf@18000 {
262		compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
263		reg = <0x18000 0x1000>;
264		interrupts = <16 2 1 31>;
265		fsl,ccf-num-csdids = <32>;
266		fsl,ccf-num-snoopids = <32>;
267	};
268
269	iommu@20000 {
270		compatible = "fsl,pamu-v1.0", "fsl,pamu";
271		reg = <0x20000 0x3000>;
272		fsl,portid-mapping = <0x8000>;
273		ranges = <0 0x20000 0x3000>;
274		#address-cells = <1>;
275		#size-cells = <1>;
276		interrupts = <
277			24 2 0 0
278			16 2 1 30>;
279
280		pamu0: pamu@0 {
281			reg = <0 0x1000>;
282			fsl,primary-cache-geometry = <32 1>;
283			fsl,secondary-cache-geometry = <128 2>;
284		};
285
286		pamu1: pamu@1000 {
287			reg = <0x1000 0x1000>;
288			fsl,primary-cache-geometry = <32 1>;
289			fsl,secondary-cache-geometry = <128 2>;
290		};
291
292		pamu2: pamu@2000 {
293			reg = <0x2000 0x1000>;
294			fsl,primary-cache-geometry = <32 1>;
295			fsl,secondary-cache-geometry = <128 2>;
296		};
297	};
298
299/include/ "qoriq-mpic4.3.dtsi"
300
301	guts: global-utilities@e0000 {
302		compatible = "fsl,t2080-device-config", "fsl,qoriq-device-config-2.0";
303		reg = <0xe0000 0xe00>;
304		fsl,has-rstcr;
305		fsl,liodn-bits = <12>;
306	};
307
308/include/ "qoriq-clockgen2.dtsi"
309	global-utilities@e1000 {
310		compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
311
312		mux0: mux0@0 {
313			#clock-cells = <0>;
314			reg = <0x0 4>;
315			compatible = "fsl,qoriq-core-mux-2.0";
316			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
317				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
318			clock-names = "pll0", "pll0-div2", "pll1-div4",
319				"pll1", "pll1-div2", "pll1-div4";
320			clock-output-names = "cmux0";
321		};
322
323		mux1: mux1@20 {
324			#clock-cells = <0>;
325			reg = <0x20 4>;
326			compatible = "fsl,qoriq-core-mux-2.0";
327			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
328				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
329			clock-names = "pll0", "pll0-div2", "pll1-div4",
330				"pll1", "pll1-div2", "pll1-div4";
331			clock-output-names = "cmux1";
332		};
333	};
334
335	rcpm: global-utilities@e2000 {
336		compatible = "fsl,t2080-rcpm", "fsl,qoriq-rcpm-2.0";
337		reg = <0xe2000 0x1000>;
338	};
339
340	sfp: sfp@e8000 {
341		compatible = "fsl,t2080-sfp";
342		reg = <0xe8000 0x1000>;
343	};
344
345	serdes: serdes@ea000 {
346		compatible = "fsl,t2080-serdes";
347		reg = <0xea000 0x4000>;
348	};
349
350/include/ "elo3-dma-0.dtsi"
351	dma@100300 {
352		fsl,iommu-parent = <&pamu0>;
353		fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
354	};
355/include/ "elo3-dma-1.dtsi"
356	dma@101300 {
357		fsl,iommu-parent = <&pamu0>;
358		fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
359	};
360/include/ "elo3-dma-2.dtsi"
361	dma@102300 {
362		fsl,iommu-parent = <&pamu0>;
363		fsl,liodn-reg = <&guts 0x588>; /* DMA3LIODNR */
364	};
365
366/include/ "qoriq-espi-0.dtsi"
367	spi@110000 {
368		fsl,espi-num-chipselects = <4>;
369	};
370
371/include/ "qoriq-esdhc-0.dtsi"
372	sdhc@114000 {
373		compatible = "fsl,t2080-esdhc", "fsl,esdhc";
374		fsl,iommu-parent = <&pamu1>;
375		fsl,liodn-reg = <&guts 0x530>; /* SDMMCLIODNR */
376		sdhci,auto-cmd12;
377	};
378/include/ "qoriq-i2c-0.dtsi"
379/include/ "qoriq-i2c-1.dtsi"
380/include/ "qoriq-duart-0.dtsi"
381/include/ "qoriq-duart-1.dtsi"
382/include/ "qoriq-gpio-0.dtsi"
383/include/ "qoriq-gpio-1.dtsi"
384/include/ "qoriq-gpio-2.dtsi"
385/include/ "qoriq-gpio-3.dtsi"
386/include/ "qoriq-usb2-mph-0.dtsi"
387	usb0: usb@210000 {
388		compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
389		fsl,iommu-parent = <&pamu1>;
390		fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
391		phy_type = "utmi";
392		port0;
393	};
394/include/ "qoriq-usb2-dr-0.dtsi"
395	usb1: usb@211000 {
396		compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
397		fsl,iommu-parent = <&pamu1>;
398		fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */
399		dr_mode = "host";
400		phy_type = "utmi";
401	};
402/include/ "qoriq-sec5.2-0.dtsi"
403
404	L2_1: l2-cache-controller@c20000 {
405		/* Cluster 0 L2 cache */
406		compatible = "fsl,t2080-l2-cache-controller";
407		reg = <0xc20000 0x40000>;
408		next-level-cache = <&cpc>;
409	};
410};
411