1/* 2 * T1024 RDB Device Tree Source 3 * 4 * Copyright 2014 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "t102xsi-pre.dtsi" 36 37/ { 38 model = "fsl,T1024RDB"; 39 compatible = "fsl,T1024RDB"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 ifc: localbus@ffe124000 { 45 reg = <0xf 0xfe124000 0 0x2000>; 46 ranges = <0 0 0xf 0xe8000000 0x08000000 47 2 0 0xf 0xff800000 0x00010000 48 3 0 0xf 0xffdf0000 0x00008000>; 49 50 nor@0,0 { 51 #address-cells = <1>; 52 #size-cells = <1>; 53 compatible = "cfi-flash"; 54 reg = <0x0 0x0 0x8000000>; 55 bank-width = <2>; 56 device-width = <1>; 57 }; 58 59 nand@1,0 { 60 #address-cells = <1>; 61 #size-cells = <1>; 62 compatible = "fsl,ifc-nand"; 63 reg = <0x2 0x0 0x10000>; 64 }; 65 66 board-control@2,0 { 67 #address-cells = <1>; 68 #size-cells = <1>; 69 compatible = "fsl,t1024-cpld"; 70 reg = <3 0 0x300>; 71 ranges = <0 3 0 0x300>; 72 bank-width = <1>; 73 device-width = <1>; 74 }; 75 }; 76 77 memory { 78 device_type = "memory"; 79 }; 80 81 dcsr: dcsr@f00000000 { 82 ranges = <0x00000000 0xf 0x00000000 0x01072000>; 83 }; 84 85 soc: soc@ffe000000 { 86 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 87 reg = <0xf 0xfe000000 0 0x00001000>; 88 spi@110000 { 89 flash@0 { 90 #address-cells = <1>; 91 #size-cells = <1>; 92 compatible = "micron,n25q512ax3", "jedec,spi-nor"; 93 reg = <0>; 94 spi-max-frequency = <10000000>; /* input clk */ 95 }; 96 97 slic@1 { 98 compatible = "maxim,ds26522"; 99 reg = <1>; 100 spi-max-frequency = <2000000>; 101 }; 102 103 slic@2 { 104 compatible = "maxim,ds26522"; 105 reg = <2>; 106 spi-max-frequency = <2000000>; 107 }; 108 }; 109 110 i2c@118000 { 111 adt7461@4c { 112 /* Thermal Monitor */ 113 compatible = "adi,adt7461"; 114 reg = <0x4c>; 115 }; 116 117 current-sensor@40 { 118 compatible = "ti,ina220"; 119 reg = <0x40>; 120 shunt-resistor = <1000>; 121 }; 122 123 eeprom@50 { 124 compatible = "atmel,24c256"; 125 reg = <0x50>; 126 }; 127 128 rtc@68 { 129 compatible = "dallas,ds1339"; 130 reg = <0x68>; 131 interrupts = <0x1 0x1 0 0>; 132 }; 133 }; 134 135 i2c@118100 { 136 pca9546@77 { 137 compatible = "nxp,pca9546"; 138 reg = <0x77>; 139 #address-cells = <1>; 140 #size-cells = <0>; 141 }; 142 }; 143 144 fman@400000 { 145 fm1mac1: ethernet@e0000 { 146 phy-handle = <&xg_aqr105_phy3>; 147 phy-connection-type = "xgmii"; 148 sleep = <&rcpm 0x80000000>; 149 }; 150 151 fm1mac2: ethernet@e2000 { 152 sleep = <&rcpm 0x40000000>; 153 }; 154 155 fm1mac3: ethernet@e4000 { 156 phy-handle = <&rgmii_phy2>; 157 phy-connection-type = "rgmii"; 158 sleep = <&rcpm 0x20000000>; 159 }; 160 161 fm1mac4: ethernet@e6000 { 162 phy-handle = <&rgmii_phy1>; 163 phy-connection-type = "rgmii"; 164 sleep = <&rcpm 0x10000000>; 165 }; 166 167 168 mdio0: mdio@fc000 { 169 rgmii_phy1: ethernet-phy@2 { 170 reg = <0x2>; 171 }; 172 rgmii_phy2: ethernet-phy@6 { 173 reg = <0x6>; 174 }; 175 }; 176 177 xmdio0: mdio@fd000 { 178 xg_aqr105_phy3: ethernet-phy@1 { 179 compatible = "ethernet-phy-ieee802.3-c45"; 180 reg = <0x1>; 181 }; 182 sg_2500_aqr105_phy4: ethernet-phy@2 { 183 compatible = "ethernet-phy-ieee802.3-c45"; 184 reg = <0x2>; 185 }; 186 }; 187 }; 188 }; 189 190 pci0: pcie@ffe240000 { 191 reg = <0xf 0xfe240000 0 0x10000>; 192 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000 193 0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>; 194 pcie@0 { 195 ranges = <0x02000000 0 0xe0000000 196 0x02000000 0 0xe0000000 197 0 0x10000000 198 199 0x01000000 0 0x00000000 200 0x01000000 0 0x00000000 201 0 0x00010000>; 202 }; 203 }; 204 205 pci1: pcie@ffe250000 { 206 reg = <0xf 0xfe250000 0 0x10000>; 207 ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 208 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>; 209 pcie@0 { 210 ranges = <0x02000000 0 0xe0000000 211 0x02000000 0 0xe0000000 212 0 0x10000000 213 214 0x01000000 0 0x00000000 215 0x01000000 0 0x00000000 216 0 0x00010000>; 217 }; 218 }; 219 220 pci2: pcie@ffe260000 { 221 reg = <0xf 0xfe260000 0 0x10000>; 222 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 223 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 224 pcie@0 { 225 ranges = <0x02000000 0 0xe0000000 226 0x02000000 0 0xe0000000 227 0 0x10000000 228 229 0x01000000 0 0x00000000 230 0x01000000 0 0x00000000 231 0 0x00010000>; 232 }; 233 }; 234}; 235 236#include "t1024si-post.dtsi" 237