1/* 2 * T1023 RDB Device Tree Source 3 * 4 * Copyright 2014 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "t102xsi-pre.dtsi" 36 37/ { 38 model = "fsl,T1023RDB"; 39 compatible = "fsl,T1023RDB"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 ifc: localbus@ffe124000 { 45 reg = <0xf 0xfe124000 0 0x2000>; 46 ranges = <0 0 0xf 0xe8000000 0x08000000 47 1 0 0xf 0xff800000 0x00010000>; 48 49 nor@0,0 { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 status = "disabled"; 53 compatible = "cfi-flash"; 54 reg = <0x0 0x0 0x8000000>; 55 bank-width = <2>; 56 device-width = <1>; 57 }; 58 59 nand@1,0 { 60 #address-cells = <1>; 61 #size-cells = <1>; 62 compatible = "fsl,ifc-nand"; 63 reg = <0x1 0x0 0x10000>; 64 }; 65 }; 66 67 memory { 68 device_type = "memory"; 69 }; 70 71 dcsr: dcsr@f00000000 { 72 ranges = <0x00000000 0xf 0x00000000 0x01072000>; 73 }; 74 75 soc: soc@ffe000000 { 76 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 77 reg = <0xf 0xfe000000 0 0x00001000>; 78 spi@110000 { 79 flash@0 { 80 #address-cells = <1>; 81 #size-cells = <1>; 82 compatible = "spansion,s25fl512s", "jedec,spi-nor"; 83 reg = <0>; 84 spi-max-frequency = <10000000>; /* input clk */ 85 }; 86 }; 87 88 i2c@118000 { 89 eeprom@50 { 90 compatible = "st,m24256"; 91 reg = <0x50>; 92 }; 93 94 rtc@68 { 95 compatible = "dallas,ds1339"; 96 reg = <0x68>; 97 interrupts = <0x5 0x1 0 0>; 98 }; 99 }; 100 101 i2c@118100 { 102 current-sensor@40 { 103 compatible = "ti,ina220"; 104 reg = <0x40>; 105 shunt-resistor = <1000>; 106 }; 107 108 current-sensor@41 { 109 compatible = "ti,ina220"; 110 reg = <0x41>; 111 shunt-resistor = <1000>; 112 }; 113 }; 114 115 fman@400000 { 116 fm1mac1: ethernet@e0000 { 117 phy-handle = <&sgmii_rtk_phy2>; 118 phy-connection-type = "sgmii"; 119 sleep = <&rcpm 0x80000000>; 120 }; 121 122 fm1mac2: ethernet@e2000 { 123 sleep = <&rcpm 0x40000000>; 124 }; 125 126 fm1mac3: ethernet@e4000 { 127 phy-handle = <&sgmii_aqr_phy3>; 128 phy-connection-type = "sgmii-2500"; 129 sleep = <&rcpm 0x20000000>; 130 }; 131 132 fm1mac4: ethernet@e6000 { 133 phy-handle = <&rgmii_rtk_phy1>; 134 phy-connection-type = "rgmii"; 135 sleep = <&rcpm 0x10000000>; 136 }; 137 138 139 mdio0: mdio@fc000 { 140 rgmii_rtk_phy1: ethernet-phy@1 { 141 reg = <0x1>; 142 }; 143 sgmii_rtk_phy2: ethernet-phy@3 { 144 reg = <0x3>; 145 }; 146 }; 147 148 xmdio0: mdio@fd000 { 149 sgmii_aqr_phy3: ethernet-phy@2 { 150 compatible = "ethernet-phy-ieee802.3-c45"; 151 reg = <0x2>; 152 }; 153 }; 154 }; 155 }; 156 157 pci0: pcie@ffe240000 { 158 reg = <0xf 0xfe240000 0 0x10000>; 159 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000 160 0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>; 161 pcie@0 { 162 ranges = <0x02000000 0 0xe0000000 163 0x02000000 0 0xe0000000 164 0 0x10000000 165 166 0x01000000 0 0x00000000 167 0x01000000 0 0x00000000 168 0 0x00010000>; 169 }; 170 }; 171 172 pci1: pcie@ffe250000 { 173 reg = <0xf 0xfe250000 0 0x10000>; 174 ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 175 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>; 176 pcie@0 { 177 ranges = <0x02000000 0 0xe0000000 178 0x02000000 0 0xe0000000 179 0 0x10000000 180 181 0x01000000 0 0x00000000 182 0x01000000 0 0x00000000 183 0 0x00010000>; 184 }; 185 }; 186 187 pci2: pcie@ffe260000 { 188 reg = <0xf 0xfe260000 0 0x10000>; 189 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 190 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 191 pcie@0 { 192 ranges = <0x02000000 0 0xe0000000 193 0x02000000 0 0xe0000000 194 0 0x10000000 195 196 0x01000000 0 0x00000000 197 0x01000000 0 0x00000000 198 0 0x00010000>; 199 }; 200 }; 201}; 202 203#include "t1023si-post.dtsi" 204