1/*
2 * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *	 notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *	 notice, this list of conditions and the following disclaimer in the
12 *	 documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *	 names of its contributors may be used to endorse or promote products
15 *	 derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35clockgen: global-utilities@e1000 {
36	compatible = "fsl,qoriq-clockgen-1.0";
37	ranges = <0x0 0xe1000 0x1000>;
38	reg = <0xe1000 0x1000>;
39	clock-frequency = <0>;
40	#address-cells = <1>;
41	#size-cells = <1>;
42	#clock-cells = <2>;
43
44	sysclk: sysclk {
45		#clock-cells = <0>;
46		compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
47		clock-output-names = "sysclk";
48	};
49	pll0: pll0@800 {
50		#clock-cells = <1>;
51		reg = <0x800 0x4>;
52		compatible = "fsl,qoriq-core-pll-1.0";
53		clocks = <&sysclk>;
54		clock-output-names = "pll0", "pll0-div2";
55	};
56	pll1: pll1@820 {
57		#clock-cells = <1>;
58		reg = <0x820 0x4>;
59		compatible = "fsl,qoriq-core-pll-1.0";
60		clocks = <&sysclk>;
61		clock-output-names = "pll1", "pll1-div2";
62	};
63	mux0: mux0@0 {
64		#clock-cells = <0>;
65		reg = <0x0 0x4>;
66		compatible = "fsl,qoriq-core-mux-1.0";
67		clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
68		clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
69		clock-output-names = "cmux0";
70	};
71	mux1: mux1@20 {
72		#clock-cells = <0>;
73		reg = <0x20 0x4>;
74		compatible = "fsl,qoriq-core-mux-1.0";
75		clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
76		clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
77		clock-output-names = "cmux1";
78	};
79	platform_pll: platform-pll@c00 {
80		#clock-cells = <1>;
81		reg = <0xc00 0x4>;
82		compatible = "fsl,qoriq-platform-pll-1.0";
83		clocks = <&sysclk>;
84		clock-output-names = "platform-pll", "platform-pll-div2";
85	};
86};
87