1/* 2 * P5020DS Device Tree Source 3 * 4 * Copyright 2010 - 2014 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "p5020si-pre.dtsi" 36 37/ { 38 model = "fsl,P5020DS"; 39 compatible = "fsl,P5020DS"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 memory { 45 device_type = "memory"; 46 }; 47 48 reserved-memory { 49 #address-cells = <2>; 50 #size-cells = <2>; 51 ranges; 52 53 bman_fbpr: bman-fbpr { 54 size = <0 0x1000000>; 55 alignment = <0 0x1000000>; 56 }; 57 qman_fqd: qman-fqd { 58 size = <0 0x400000>; 59 alignment = <0 0x400000>; 60 }; 61 qman_pfdr: qman-pfdr { 62 size = <0 0x2000000>; 63 alignment = <0 0x2000000>; 64 }; 65 }; 66 67 dcsr: dcsr@f00000000 { 68 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 69 }; 70 71 bportals: bman-portals@ff4000000 { 72 ranges = <0x0 0xf 0xf4000000 0x200000>; 73 }; 74 75 qportals: qman-portals@ff4200000 { 76 ranges = <0x0 0xf 0xf4200000 0x200000>; 77 }; 78 79 soc: soc@ffe000000 { 80 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 81 reg = <0xf 0xfe000000 0 0x00001000>; 82 spi@110000 { 83 flash@0 { 84 #address-cells = <1>; 85 #size-cells = <1>; 86 compatible = "spansion,s25sl12801"; 87 reg = <0>; 88 spi-max-frequency = <40000000>; /* input clock */ 89 partition@u-boot { 90 label = "u-boot"; 91 reg = <0x00000000 0x00100000>; 92 read-only; 93 }; 94 partition@kernel { 95 label = "kernel"; 96 reg = <0x00100000 0x00500000>; 97 read-only; 98 }; 99 partition@dtb { 100 label = "dtb"; 101 reg = <0x00600000 0x00100000>; 102 read-only; 103 }; 104 partition@fs { 105 label = "file system"; 106 reg = <0x00700000 0x00900000>; 107 }; 108 }; 109 }; 110 111 i2c@118100 { 112 eeprom@51 { 113 compatible = "at24,24c256"; 114 reg = <0x51>; 115 }; 116 eeprom@52 { 117 compatible = "at24,24c256"; 118 reg = <0x52>; 119 }; 120 }; 121 122 i2c@119100 { 123 rtc@68 { 124 compatible = "dallas,ds3232"; 125 reg = <0x68>; 126 interrupts = <0x1 0x1 0 0>; 127 }; 128 ina220@40 { 129 compatible = "ti,ina220"; 130 reg = <0x40>; 131 shunt-resistor = <1000>; 132 }; 133 ina220@41 { 134 compatible = "ti,ina220"; 135 reg = <0x41>; 136 shunt-resistor = <1000>; 137 }; 138 ina220@44 { 139 compatible = "ti,ina220"; 140 reg = <0x44>; 141 shunt-resistor = <1000>; 142 }; 143 ina220@45 { 144 compatible = "ti,ina220"; 145 reg = <0x45>; 146 shunt-resistor = <1000>; 147 }; 148 adt7461@4c { 149 compatible = "adi,adt7461"; 150 reg = <0x4c>; 151 }; 152 }; 153 }; 154 155 rio: rapidio@ffe0c0000 { 156 reg = <0xf 0xfe0c0000 0 0x11000>; 157 158 port1 { 159 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 160 }; 161 port2 { 162 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 163 }; 164 }; 165 166 lbc: localbus@ffe124000 { 167 reg = <0xf 0xfe124000 0 0x1000>; 168 ranges = <0 0 0xf 0xe8000000 0x08000000 169 2 0 0xf 0xffa00000 0x00040000 170 3 0 0xf 0xffdf0000 0x00008000>; 171 172 flash@0,0 { 173 compatible = "cfi-flash"; 174 reg = <0 0 0x08000000>; 175 bank-width = <2>; 176 device-width = <2>; 177 }; 178 179 nand@2,0 { 180 #address-cells = <1>; 181 #size-cells = <1>; 182 compatible = "fsl,elbc-fcm-nand"; 183 reg = <0x2 0x0 0x40000>; 184 185 partition@0 { 186 label = "NAND U-Boot Image"; 187 reg = <0x0 0x02000000>; 188 read-only; 189 }; 190 191 partition@2000000 { 192 label = "NAND Root File System"; 193 reg = <0x02000000 0x10000000>; 194 }; 195 196 partition@12000000 { 197 label = "NAND Compressed RFS Image"; 198 reg = <0x12000000 0x08000000>; 199 }; 200 201 partition@1a000000 { 202 label = "NAND Linux Kernel Image"; 203 reg = <0x1a000000 0x04000000>; 204 }; 205 206 partition@1e000000 { 207 label = "NAND DTB Image"; 208 reg = <0x1e000000 0x01000000>; 209 }; 210 211 partition@1f000000 { 212 label = "NAND Writable User area"; 213 reg = <0x1f000000 0x21000000>; 214 }; 215 }; 216 217 board-control@3,0 { 218 compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis"; 219 reg = <3 0 0x30>; 220 }; 221 }; 222 223 pci0: pcie@ffe200000 { 224 reg = <0xf 0xfe200000 0 0x1000>; 225 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 226 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 227 pcie@0 { 228 ranges = <0x02000000 0 0xe0000000 229 0x02000000 0 0xe0000000 230 0 0x20000000 231 232 0x01000000 0 0x00000000 233 0x01000000 0 0x00000000 234 0 0x00010000>; 235 }; 236 }; 237 238 pci1: pcie@ffe201000 { 239 reg = <0xf 0xfe201000 0 0x1000>; 240 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 241 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 242 pcie@0 { 243 ranges = <0x02000000 0 0xe0000000 244 0x02000000 0 0xe0000000 245 0 0x20000000 246 247 0x01000000 0 0x00000000 248 0x01000000 0 0x00000000 249 0 0x00010000>; 250 }; 251 }; 252 253 pci2: pcie@ffe202000 { 254 reg = <0xf 0xfe202000 0 0x1000>; 255 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 256 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 257 pcie@0 { 258 ranges = <0x02000000 0 0xe0000000 259 0x02000000 0 0xe0000000 260 0 0x20000000 261 262 0x01000000 0 0x00000000 263 0x01000000 0 0x00000000 264 0 0x00010000>; 265 }; 266 }; 267 268 pci3: pcie@ffe203000 { 269 reg = <0xf 0xfe203000 0 0x1000>; 270 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 271 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 272 pcie@0 { 273 ranges = <0x02000000 0 0xe0000000 274 0x02000000 0 0xe0000000 275 0 0x20000000 276 277 0x01000000 0 0x00000000 278 0x01000000 0 0x00000000 279 0 0x00010000>; 280 }; 281 }; 282}; 283 284/include/ "p5020si-post.dtsi" 285