1/* 2 * P4080DS Device Tree Source 3 * 4 * Copyright 2009 - 2015 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "p4080si-pre.dtsi" 36 37/ { 38 model = "fsl,P4080DS"; 39 compatible = "fsl,P4080DS"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 aliases { 45 phy_rgmii = &phyrgmii; 46 phy5_slot3 = &phy5slot3; 47 phy6_slot3 = &phy6slot3; 48 phy7_slot3 = &phy7slot3; 49 phy8_slot3 = &phy8slot3; 50 emi1_slot3 = &p4080mdio2; 51 emi1_slot4 = &p4080mdio1; 52 emi1_slot5 = &p4080mdio3; 53 emi1_rgmii = &p4080mdio0; 54 emi2_slot4 = &p4080xmdio1; 55 emi2_slot5 = &p4080xmdio3; 56 }; 57 58 memory { 59 device_type = "memory"; 60 }; 61 62 reserved-memory { 63 #address-cells = <2>; 64 #size-cells = <2>; 65 ranges; 66 67 bman_fbpr: bman-fbpr { 68 size = <0 0x1000000>; 69 alignment = <0 0x1000000>; 70 }; 71 qman_fqd: qman-fqd { 72 size = <0 0x400000>; 73 alignment = <0 0x400000>; 74 }; 75 qman_pfdr: qman-pfdr { 76 size = <0 0x2000000>; 77 alignment = <0 0x2000000>; 78 }; 79 }; 80 81 dcsr: dcsr@f00000000 { 82 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 83 }; 84 85 bportals: bman-portals@ff4000000 { 86 ranges = <0x0 0xf 0xf4000000 0x200000>; 87 }; 88 89 qportals: qman-portals@ff4200000 { 90 ranges = <0x0 0xf 0xf4200000 0x200000>; 91 }; 92 93 soc: soc@ffe000000 { 94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 95 reg = <0xf 0xfe000000 0 0x00001000>; 96 97 spi@110000 { 98 flash@0 { 99 #address-cells = <1>; 100 #size-cells = <1>; 101 compatible = "spansion,s25sl12801", "jedec,spi-nor"; 102 reg = <0>; 103 spi-max-frequency = <40000000>; /* input clock */ 104 partition@u-boot { 105 label = "u-boot"; 106 reg = <0x00000000 0x00100000>; 107 read-only; 108 }; 109 partition@kernel { 110 label = "kernel"; 111 reg = <0x00100000 0x00500000>; 112 read-only; 113 }; 114 partition@dtb { 115 label = "dtb"; 116 reg = <0x00600000 0x00100000>; 117 read-only; 118 }; 119 partition@fs { 120 label = "file system"; 121 reg = <0x00700000 0x00900000>; 122 }; 123 }; 124 }; 125 126 i2c@118100 { 127 eeprom@51 { 128 compatible = "atmel,24c256"; 129 reg = <0x51>; 130 }; 131 eeprom@52 { 132 compatible = "atmel,24c256"; 133 reg = <0x52>; 134 }; 135 rtc@68 { 136 compatible = "dallas,ds3232"; 137 reg = <0x68>; 138 interrupts = <0x1 0x1 0 0>; 139 }; 140 adt7461@4c { 141 compatible = "adi,adt7461"; 142 reg = <0x4c>; 143 }; 144 }; 145 146 usb0: usb@210000 { 147 phy_type = "ulpi"; 148 }; 149 150 usb1: usb@211000 { 151 dr_mode = "host"; 152 phy_type = "ulpi"; 153 }; 154 155 fman@400000 { 156 ethernet@e0000 { 157 phy-handle = <&phy0>; 158 phy-connection-type = "sgmii"; 159 }; 160 161 ethernet@e2000 { 162 phy-handle = <&phy1>; 163 phy-connection-type = "sgmii"; 164 }; 165 166 ethernet@e4000 { 167 phy-handle = <&phy2>; 168 phy-connection-type = "sgmii"; 169 }; 170 171 ethernet@e6000 { 172 phy-handle = <&phy3>; 173 phy-connection-type = "sgmii"; 174 }; 175 176 ethernet@f0000 { 177 phy-handle = <&phy10>; 178 phy-connection-type = "xgmii"; 179 }; 180 }; 181 182 fman@500000 { 183 ethernet@e0000 { 184 phy-handle = <&phy5>; 185 phy-connection-type = "sgmii"; 186 }; 187 188 ethernet@e2000 { 189 phy-handle = <&phy6>; 190 phy-connection-type = "sgmii"; 191 }; 192 193 ethernet@e4000 { 194 phy-handle = <&phy7>; 195 phy-connection-type = "sgmii"; 196 }; 197 198 ethernet@e6000 { 199 phy-handle = <&phy8>; 200 phy-connection-type = "sgmii"; 201 }; 202 203 ethernet@f0000 { 204 phy-handle = <&phy11>; 205 phy-connection-type = "xgmii"; 206 }; 207 }; 208 }; 209 210 rio: rapidio@ffe0c0000 { 211 reg = <0xf 0xfe0c0000 0 0x11000>; 212 213 port1 { 214 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 215 }; 216 port2 { 217 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 218 }; 219 }; 220 221 lbc: localbus@ffe124000 { 222 reg = <0xf 0xfe124000 0 0x1000>; 223 ranges = <0 0 0xf 0xe8000000 0x08000000 224 3 0 0xf 0xffdf0000 0x00008000>; 225 226 flash@0,0 { 227 compatible = "cfi-flash"; 228 reg = <0 0 0x08000000>; 229 bank-width = <2>; 230 device-width = <2>; 231 }; 232 233 board-control@3,0 { 234 compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis"; 235 reg = <3 0 0x30>; 236 }; 237 }; 238 239 pci0: pcie@ffe200000 { 240 reg = <0xf 0xfe200000 0 0x1000>; 241 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 242 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 243 pcie@0 { 244 ranges = <0x02000000 0 0xe0000000 245 0x02000000 0 0xe0000000 246 0 0x20000000 247 248 0x01000000 0 0x00000000 249 0x01000000 0 0x00000000 250 0 0x00010000>; 251 }; 252 }; 253 254 pci1: pcie@ffe201000 { 255 reg = <0xf 0xfe201000 0 0x1000>; 256 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 257 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 258 pcie@0 { 259 ranges = <0x02000000 0 0xe0000000 260 0x02000000 0 0xe0000000 261 0 0x20000000 262 263 0x01000000 0 0x00000000 264 0x01000000 0 0x00000000 265 0 0x00010000>; 266 }; 267 }; 268 269 pci2: pcie@ffe202000 { 270 reg = <0xf 0xfe202000 0 0x1000>; 271 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 272 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 273 pcie@0 { 274 ranges = <0x02000000 0 0xe0000000 275 0x02000000 0 0xe0000000 276 0 0x20000000 277 278 0x01000000 0 0x00000000 279 0x01000000 0 0x00000000 280 0 0x00010000>; 281 }; 282 }; 283 284 mdio-mux-emi1 { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 compatible = "mdio-mux-gpio", "mdio-mux"; 288 mdio-parent-bus = <&mdio0>; 289 gpios = <&gpio0 1 0>, <&gpio0 0 0>; 290 291 p4080mdio0: mdio@0 { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 reg = <0>; 295 296 phyrgmii: ethernet-phy@0 { 297 reg = <0x0>; 298 }; 299 }; 300 301 p4080mdio1: mdio@1 { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 reg = <1>; 305 306 phy5: ethernet-phy@1c { 307 reg = <0x1c>; 308 }; 309 310 phy6: ethernet-phy@1d { 311 reg = <0x1d>; 312 }; 313 314 phy7: ethernet-phy@1e { 315 reg = <0x1e>; 316 }; 317 318 phy8: ethernet-phy@1f { 319 reg = <0x1f>; 320 }; 321 }; 322 323 p4080mdio2: mdio@2 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 reg = <2>; 327 status = "disabled"; 328 329 phy5slot3: ethernet-phy@1c { 330 reg = <0x1c>; 331 }; 332 333 phy6slot3: ethernet-phy@1d { 334 reg = <0x1d>; 335 }; 336 337 phy7slot3: ethernet-phy@1e { 338 reg = <0x1e>; 339 }; 340 341 phy8slot3: ethernet-phy@1f { 342 reg = <0x1f>; 343 }; 344 }; 345 346 p4080mdio3: mdio@3 { 347 #address-cells = <1>; 348 #size-cells = <0>; 349 reg = <3>; 350 351 phy0: ethernet-phy@1c { 352 reg = <0x1c>; 353 }; 354 355 phy1: ethernet-phy@1d { 356 reg = <0x1d>; 357 }; 358 359 phy2: ethernet-phy@1e { 360 reg = <0x1e>; 361 }; 362 363 phy3: ethernet-phy@1f { 364 reg = <0x1f>; 365 }; 366 }; 367 }; 368 369 mdio-mux-emi2 { 370 #address-cells = <1>; 371 #size-cells = <0>; 372 compatible = "mdio-mux-gpio", "mdio-mux"; 373 mdio-parent-bus = <&xmdio0>; 374 gpios = <&gpio0 3 0>, <&gpio0 2 0>; 375 376 p4080xmdio1: mdio@1 { 377 #address-cells = <1>; 378 #size-cells = <0>; 379 reg = <1>; 380 381 phy11: ethernet-phy@0 { 382 compatible = "ethernet-phy-ieee802.3-c45"; 383 reg = <0x0>; 384 }; 385 }; 386 387 p4080xmdio3: mdio@3 { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 reg = <3>; 391 392 phy10: ethernet-phy@4 { 393 compatible = "ethernet-phy-ieee802.3-c45"; 394 reg = <0x4>; 395 }; 396 }; 397 }; 398}; 399 400/include/ "p4080si-post.dtsi" 401