1/*
2 * P3041 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&bman_fbpr {
36	compatible = "fsl,bman-fbpr";
37	alloc-ranges = <0 0 0x10 0>;
38};
39
40&qman_fqd {
41	compatible = "fsl,qman-fqd";
42	alloc-ranges = <0 0 0x10 0>;
43};
44
45&qman_pfdr {
46	compatible = "fsl,qman-pfdr";
47	alloc-ranges = <0 0 0x10 0>;
48};
49
50&lbc {
51	compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
52	interrupts = <25 2 0 0>;
53	#address-cells = <2>;
54	#size-cells = <1>;
55};
56
57/* controller at 0x200000 */
58&pci0 {
59	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
60	device_type = "pci";
61	#size-cells = <2>;
62	#address-cells = <3>;
63	bus-range = <0x0 0xff>;
64	clock-frequency = <33333333>;
65	interrupts = <16 2 1 15>;
66	fsl,iommu-parent = <&pamu0>;
67	fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
68	pcie@0 {
69		reg = <0 0 0 0 0>;
70		#interrupt-cells = <1>;
71		#size-cells = <2>;
72		#address-cells = <3>;
73		device_type = "pci";
74		interrupts = <16 2 1 15>;
75		interrupt-map-mask = <0xf800 0 0 7>;
76		interrupt-map = <
77			/* IDSEL 0x0 */
78			0000 0 0 1 &mpic 40 1 0 0
79			0000 0 0 2 &mpic 1 1 0 0
80			0000 0 0 3 &mpic 2 1 0 0
81			0000 0 0 4 &mpic 3 1 0 0
82			>;
83	};
84};
85
86/* controller at 0x201000 */
87&pci1 {
88	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
89	device_type = "pci";
90	#size-cells = <2>;
91	#address-cells = <3>;
92	bus-range = <0 0xff>;
93	clock-frequency = <33333333>;
94	interrupts = <16 2 1 14>;
95	fsl,iommu-parent = <&pamu0>;
96	fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
97	pcie@0 {
98		reg = <0 0 0 0 0>;
99		#interrupt-cells = <1>;
100		#size-cells = <2>;
101		#address-cells = <3>;
102		device_type = "pci";
103		interrupts = <16 2 1 14>;
104		interrupt-map-mask = <0xf800 0 0 7>;
105		interrupt-map = <
106			/* IDSEL 0x0 */
107			0000 0 0 1 &mpic 41 1 0 0
108			0000 0 0 2 &mpic 5 1 0 0
109			0000 0 0 3 &mpic 6 1 0 0
110			0000 0 0 4 &mpic 7 1 0 0
111			>;
112	};
113};
114
115/* controller at 0x202000 */
116&pci2 {
117	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
118	device_type = "pci";
119	#size-cells = <2>;
120	#address-cells = <3>;
121	bus-range = <0x0 0xff>;
122	clock-frequency = <33333333>;
123	interrupts = <16 2 1 13>;
124	fsl,iommu-parent = <&pamu0>;
125	fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
126	pcie@0 {
127		reg = <0 0 0 0 0>;
128		#interrupt-cells = <1>;
129		#size-cells = <2>;
130		#address-cells = <3>;
131		device_type = "pci";
132		interrupts = <16 2 1 13>;
133		interrupt-map-mask = <0xf800 0 0 7>;
134		interrupt-map = <
135			/* IDSEL 0x0 */
136			0000 0 0 1 &mpic 42 1 0 0
137			0000 0 0 2 &mpic 9 1 0 0
138			0000 0 0 3 &mpic 10 1 0 0
139			0000 0 0 4 &mpic 11 1 0 0
140			>;
141	};
142};
143
144/* controller at 0x203000 */
145&pci3 {
146	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
147	device_type = "pci";
148	#size-cells = <2>;
149	#address-cells = <3>;
150	bus-range = <0x0 0xff>;
151	clock-frequency = <33333333>;
152	interrupts = <16 2 1 12>;
153	pcie@0 {
154		reg = <0 0 0 0 0>;
155		#interrupt-cells = <1>;
156		#size-cells = <2>;
157		#address-cells = <3>;
158		device_type = "pci";
159		interrupts = <16 2 1 12>;
160		interrupt-map-mask = <0xf800 0 0 7>;
161		interrupt-map = <
162			/* IDSEL 0x0 */
163			0000 0 0 1 &mpic 43 1 0 0
164			0000 0 0 2 &mpic 0 1 0 0
165			0000 0 0 3 &mpic 4 1 0 0
166			0000 0 0 4 &mpic 8 1 0 0
167			>;
168	};
169};
170
171&rio {
172	compatible = "fsl,srio";
173	interrupts = <16 2 1 11>;
174	#address-cells = <2>;
175	#size-cells = <2>;
176	fsl,iommu-parent = <&pamu0>;
177	ranges;
178
179	port1 {
180		#address-cells = <2>;
181		#size-cells = <2>;
182		cell-index = <1>;
183		fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
184	};
185
186	port2 {
187		#address-cells = <2>;
188		#size-cells = <2>;
189		cell-index = <2>;
190		fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
191	};
192};
193
194&dcsr {
195	#address-cells = <1>;
196	#size-cells = <1>;
197	compatible = "fsl,dcsr", "simple-bus";
198
199	dcsr-epu@0 {
200		compatible = "fsl,p3041-dcsr-epu", "fsl,dcsr-epu";
201		interrupts = <52 2 0 0
202			      84 2 0 0
203			      85 2 0 0>;
204		reg = <0x0 0x1000>;
205	};
206	dcsr-npc {
207		compatible = "fsl,dcsr-npc";
208		reg = <0x1000 0x1000 0x1000000 0x8000>;
209	};
210	dcsr-nxc@2000 {
211		compatible = "fsl,dcsr-nxc";
212		reg = <0x2000 0x1000>;
213	};
214	dcsr-corenet {
215		compatible = "fsl,dcsr-corenet";
216		reg = <0x8000 0x1000 0xB0000 0x1000>;
217	};
218	dcsr-dpaa@9000 {
219		compatible = "fsl,p3041-dcsr-dpaa", "fsl,dcsr-dpaa";
220		reg = <0x9000 0x1000>;
221	};
222	dcsr-ocn@11000 {
223		compatible = "fsl,p3041-dcsr-ocn", "fsl,dcsr-ocn";
224		reg = <0x11000 0x1000>;
225	};
226	dcsr-ddr@12000 {
227		compatible = "fsl,dcsr-ddr";
228		dev-handle = <&ddr1>;
229		reg = <0x12000 0x1000>;
230	};
231	dcsr-nal@18000 {
232		compatible = "fsl,p3041-dcsr-nal", "fsl,dcsr-nal";
233		reg = <0x18000 0x1000>;
234	};
235	dcsr-rcpm@22000 {
236		compatible = "fsl,p3041-dcsr-rcpm", "fsl,dcsr-rcpm";
237		reg = <0x22000 0x1000>;
238	};
239	dcsr-cpu-sb-proxy@40000 {
240		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
241		cpu-handle = <&cpu0>;
242		reg = <0x40000 0x1000>;
243	};
244	dcsr-cpu-sb-proxy@41000 {
245		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
246		cpu-handle = <&cpu1>;
247		reg = <0x41000 0x1000>;
248	};
249	dcsr-cpu-sb-proxy@42000 {
250		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
251		cpu-handle = <&cpu2>;
252		reg = <0x42000 0x1000>;
253	};
254	dcsr-cpu-sb-proxy@43000 {
255		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
256		cpu-handle = <&cpu3>;
257		reg = <0x43000 0x1000>;
258	};
259};
260
261/include/ "qoriq-bman1-portals.dtsi"
262
263/include/ "qoriq-qman1-portals.dtsi"
264
265&soc {
266	#address-cells = <1>;
267	#size-cells = <1>;
268	device_type = "soc";
269	compatible = "simple-bus";
270
271	soc-sram-error {
272		compatible = "fsl,soc-sram-error";
273		interrupts = <16 2 1 29>;
274	};
275
276	corenet-law@0 {
277		compatible = "fsl,corenet-law";
278		reg = <0x0 0x1000>;
279		fsl,num-laws = <32>;
280	};
281
282	ddr1: memory-controller@8000 {
283		compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
284		reg = <0x8000 0x1000>;
285		interrupts = <16 2 1 23>;
286	};
287
288	cpc: l3-cache-controller@10000 {
289		compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
290		reg = <0x10000 0x1000>;
291		interrupts = <16 2 1 27>;
292	};
293
294	corenet-cf@18000 {
295		compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
296		reg = <0x18000 0x1000>;
297		interrupts = <16 2 1 31>;
298		fsl,ccf-num-csdids = <32>;
299		fsl,ccf-num-snoopids = <32>;
300	};
301
302	iommu@20000 {
303		compatible = "fsl,pamu-v1.0", "fsl,pamu";
304		reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
305		ranges = <0 0x20000 0x4000>;
306		#address-cells = <1>;
307		#size-cells = <1>;
308		interrupts = <
309			24 2 0 0
310			16 2 1 30>;
311		fsl,portid-mapping = <0x0f000000>;
312
313		pamu0: pamu@0 {
314			reg = <0 0x1000>;
315			fsl,primary-cache-geometry = <32 1>;
316			fsl,secondary-cache-geometry = <128 2>;
317		};
318
319		pamu1: pamu@1000 {
320			reg = <0x1000 0x1000>;
321			fsl,primary-cache-geometry = <32 1>;
322			fsl,secondary-cache-geometry = <128 2>;
323		};
324
325		pamu2: pamu@2000 {
326			reg = <0x2000 0x1000>;
327			fsl,primary-cache-geometry = <32 1>;
328			fsl,secondary-cache-geometry = <128 2>;
329		};
330
331		pamu3: pamu@3000 {
332			reg = <0x3000 0x1000>;
333			fsl,primary-cache-geometry = <32 1>;
334			fsl,secondary-cache-geometry = <128 2>;
335		};
336	};
337
338/include/ "qoriq-mpic.dtsi"
339
340	guts: global-utilities@e0000 {
341		compatible = "fsl,qoriq-device-config-1.0";
342		reg = <0xe0000 0xe00>;
343		fsl,has-rstcr;
344		#sleep-cells = <1>;
345		fsl,liodn-bits = <12>;
346	};
347
348	pins: global-utilities@e0e00 {
349		compatible = "fsl,qoriq-pin-control-1.0";
350		reg = <0xe0e00 0x200>;
351		#sleep-cells = <2>;
352	};
353
354/include/ "qoriq-clockgen1.dtsi"
355	global-utilities@e1000 {
356		compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
357
358		mux2: mux2@40 {
359			#clock-cells = <0>;
360			reg = <0x40 0x4>;
361			compatible = "fsl,qoriq-core-mux-1.0";
362			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
363			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
364			clock-output-names = "cmux2";
365		};
366
367		mux3: mux3@60 {
368			#clock-cells = <0>;
369			reg = <0x60 0x4>;
370			compatible = "fsl,qoriq-core-mux-1.0";
371			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
372			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
373			clock-output-names = "cmux3";
374		};
375	};
376
377	rcpm: global-utilities@e2000 {
378		compatible = "fsl,qoriq-rcpm-1.0";
379		reg = <0xe2000 0x1000>;
380		#sleep-cells = <1>;
381	};
382
383	sfp: sfp@e8000 {
384		compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
385		reg	   = <0xe8000 0x1000>;
386	};
387
388	serdes: serdes@ea000 {
389		compatible = "fsl,p3041-serdes";
390		reg	   = <0xea000 0x1000>;
391	};
392
393/include/ "qoriq-dma-0.dtsi"
394	dma@100300 {
395		fsl,iommu-parent = <&pamu0>;
396		fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
397	};
398
399/include/ "qoriq-dma-1.dtsi"
400	dma@101300 {
401		fsl,iommu-parent = <&pamu0>;
402		fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
403	};
404
405/include/ "qoriq-espi-0.dtsi"
406	spi@110000 {
407		fsl,espi-num-chipselects = <4>;
408	};
409
410/include/ "qoriq-esdhc-0.dtsi"
411	sdhc@114000 {
412		compatible = "fsl,p3041-esdhc", "fsl,esdhc";
413		fsl,iommu-parent = <&pamu1>;
414		fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
415		sdhci,auto-cmd12;
416	};
417
418/include/ "qoriq-i2c-0.dtsi"
419/include/ "qoriq-i2c-1.dtsi"
420/include/ "qoriq-duart-0.dtsi"
421/include/ "qoriq-duart-1.dtsi"
422/include/ "qoriq-gpio-0.dtsi"
423/include/ "qoriq-usb2-mph-0.dtsi"
424	usb0: usb@210000 {
425		compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph";
426		phy_type = "utmi";
427		fsl,iommu-parent = <&pamu1>;
428		fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
429		port0;
430	};
431
432/include/ "qoriq-usb2-dr-0.dtsi"
433	usb1: usb@211000 {
434		compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
435		fsl,iommu-parent = <&pamu1>;
436		fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
437		dr_mode = "host";
438		phy_type = "utmi";
439	};
440
441/include/ "qoriq-sata2-0.dtsi"
442	sata@220000 {
443		fsl,iommu-parent = <&pamu1>;
444		fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
445	};
446
447/include/ "qoriq-sata2-1.dtsi"
448	sata@221000 {
449		fsl,iommu-parent = <&pamu1>;
450		fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
451	};
452
453/include/ "qoriq-sec4.2-0.dtsi"
454crypto: crypto@300000 {
455		fsl,iommu-parent = <&pamu1>;
456	};
457
458/include/ "qoriq-qman1.dtsi"
459/include/ "qoriq-bman1.dtsi"
460
461/include/ "qoriq-fman-0.dtsi"
462/include/ "qoriq-fman-0-1g-0.dtsi"
463/include/ "qoriq-fman-0-1g-1.dtsi"
464/include/ "qoriq-fman-0-1g-2.dtsi"
465/include/ "qoriq-fman-0-1g-3.dtsi"
466/include/ "qoriq-fman-0-1g-4.dtsi"
467/include/ "qoriq-fman-0-10g-0.dtsi"
468	fman@400000 {
469		enet0: ethernet@e0000 {
470		};
471
472		enet1: ethernet@e2000 {
473		};
474
475		enet2: ethernet@e4000 {
476		};
477
478		enet3: ethernet@e6000 {
479		};
480
481		enet4: ethernet@e8000 {
482		};
483
484		enet5: ethernet@f0000 {
485		};
486	};
487};
488