1/*
2 * P2041RDB Device Tree Source
3 *
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "p2041si-pre.dtsi"
36
37/ {
38	model = "fsl,P2041RDB";
39	compatible = "fsl,P2041RDB";
40	#address-cells = <2>;
41	#size-cells = <2>;
42	interrupt-parent = <&mpic>;
43
44	aliases {
45		phy_rgmii_0 = &phy_rgmii_0;
46		phy_rgmii_1 = &phy_rgmii_1;
47		phy_sgmii_2 = &phy_sgmii_2;
48		phy_sgmii_3 = &phy_sgmii_3;
49		phy_sgmii_4 = &phy_sgmii_4;
50		phy_sgmii_1c = &phy_sgmii_1c;
51		phy_sgmii_1d = &phy_sgmii_1d;
52		phy_sgmii_1e = &phy_sgmii_1e;
53		phy_sgmii_1f = &phy_sgmii_1f;
54		phy_xgmii_2 = &phy_xgmii_2;
55	};
56
57	memory {
58		device_type = "memory";
59	};
60
61	reserved-memory {
62		#address-cells = <2>;
63		#size-cells = <2>;
64		ranges;
65
66		bman_fbpr: bman-fbpr {
67			size = <0 0x1000000>;
68			alignment = <0 0x1000000>;
69		};
70		qman_fqd: qman-fqd {
71			size = <0 0x400000>;
72			alignment = <0 0x400000>;
73		};
74		qman_pfdr: qman-pfdr {
75			size = <0 0x2000000>;
76			alignment = <0 0x2000000>;
77		};
78	};
79
80	dcsr: dcsr@f00000000 {
81		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
82	};
83
84	bportals: bman-portals@ff4000000 {
85		ranges = <0x0 0xf 0xf4000000 0x200000>;
86	};
87
88	qportals: qman-portals@ff4200000 {
89		ranges = <0x0 0xf 0xf4200000 0x200000>;
90	};
91
92	soc: soc@ffe000000 {
93		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
94		reg = <0xf 0xfe000000 0 0x00001000>;
95		spi@110000 {
96			flash@0 {
97				#address-cells = <1>;
98				#size-cells = <1>;
99				compatible = "spansion,s25sl12801", "jedec,spi-nor";
100				reg = <0>;
101				spi-max-frequency = <40000000>; /* input clock */
102				partition@u-boot {
103					label = "u-boot";
104					reg = <0x00000000 0x00100000>;
105					read-only;
106				};
107				partition@kernel {
108					label = "kernel";
109					reg = <0x00100000 0x00500000>;
110					read-only;
111				};
112				partition@dtb {
113					label = "dtb";
114					reg = <0x00600000 0x00100000>;
115					read-only;
116				};
117				partition@fs {
118					label = "file system";
119					reg = <0x00700000 0x00900000>;
120				};
121			};
122		};
123
124		i2c@118000 {
125			lm75b@48 {
126				compatible = "nxp,lm75a";
127				reg = <0x48>;
128			};
129			eeprom@50 {
130				compatible = "at24,24c256";
131				reg = <0x50>;
132			};
133			rtc@68 {
134				compatible = "pericom,pt7c4338";
135				reg = <0x68>;
136			};
137			adt7461@4c {
138				compatible = "adi,adt7461";
139				reg = <0x4c>;
140			};
141		};
142
143		i2c@118100 {
144			eeprom@50 {
145				compatible = "at24,24c256";
146				reg = <0x50>;
147			};
148		};
149
150		usb1: usb@211000 {
151			dr_mode = "host";
152		};
153
154		fman@400000 {
155			ethernet@e0000 {
156				phy-handle = <&phy_sgmii_2>;
157				phy-connection-type = "sgmii";
158			};
159
160			mdio@e1120 {
161				phy_rgmii_0: ethernet-phy@0 {
162					reg = <0x0>;
163				};
164
165				phy_rgmii_1: ethernet-phy@1 {
166					reg = <0x1>;
167				};
168
169				phy_sgmii_2: ethernet-phy@2 {
170					reg = <0x2>;
171				};
172
173				phy_sgmii_3: ethernet-phy@3 {
174					reg = <0x3>;
175				};
176
177				phy_sgmii_4: ethernet-phy@4 {
178					reg = <0x4>;
179				};
180
181				phy_sgmii_1c: ethernet-phy@1c {
182					reg = <0x1c>;
183				};
184
185				phy_sgmii_1d: ethernet-phy@1d {
186					reg = <0x1d>;
187				};
188
189				phy_sgmii_1e: ethernet-phy@1e {
190					reg = <0x1e>;
191				};
192
193				phy_sgmii_1f: ethernet-phy@1f {
194					reg = <0x1f>;
195				};
196			};
197
198			ethernet@e2000 {
199				phy-handle = <&phy_sgmii_3>;
200				phy-connection-type = "sgmii";
201			};
202
203			ethernet@e4000 {
204				phy-handle = <&phy_sgmii_4>;
205				phy-connection-type = "sgmii";
206			};
207
208			ethernet@e6000 {
209				phy-handle = <&phy_rgmii_1>;
210				phy-connection-type = "rgmii";
211			};
212
213			ethernet@e8000 {
214				phy-handle = <&phy_rgmii_0>;
215				phy-connection-type = "rgmii";
216			};
217
218			ethernet@f0000 {
219				phy-handle = <&phy_xgmii_2>;
220				phy-connection-type = "xgmii";
221			};
222
223			mdio@f1000 {
224				phy_xgmii_2: ethernet-phy@0 {
225					compatible = "ethernet-phy-ieee802.3-c45";
226					reg = <0x0>;
227				};
228			};
229		};
230	};
231
232	rio: rapidio@ffe0c0000 {
233		reg = <0xf 0xfe0c0000 0 0x11000>;
234
235		port1 {
236			ranges = <0 0 0xc 0x20000000 0 0x10000000>;
237		};
238		port2 {
239			ranges = <0 0 0xc 0x30000000 0 0x10000000>;
240		};
241	};
242
243	lbc: localbus@ffe124000 {
244		reg = <0xf 0xfe124000 0 0x1000>;
245		ranges = <0 0 0xf 0xe8000000 0x08000000
246			  1 0 0xf 0xffa00000 0x00040000>;
247
248		flash@0,0 {
249			compatible = "cfi-flash";
250			reg = <0 0 0x08000000>;
251			bank-width = <2>;
252			device-width = <2>;
253		};
254
255		nand@1,0 {
256			#address-cells = <1>;
257			#size-cells = <1>;
258			compatible = "fsl,elbc-fcm-nand";
259			reg = <0x1 0x0 0x40000>;
260
261			partition@0 {
262				label = "NAND U-Boot Image";
263				reg = <0x0 0x02000000>;
264				read-only;
265			};
266
267			partition@2000000 {
268				label = "NAND Root File System";
269				reg = <0x02000000 0x10000000>;
270			};
271
272			partition@12000000 {
273				label = "NAND Compressed RFS Image";
274				reg = <0x12000000 0x08000000>;
275			};
276
277			partition@1a000000 {
278				label = "NAND Linux Kernel Image";
279				reg = <0x1a000000 0x04000000>;
280			};
281
282			partition@1e000000 {
283				label = "NAND DTB Image";
284				reg = <0x1e000000 0x01000000>;
285			};
286
287			partition@1f000000 {
288				label = "NAND Writable User area";
289				reg = <0x1f000000 0x01000000>;
290			};
291		};
292	};
293
294	pci0: pcie@ffe200000 {
295		reg = <0xf 0xfe200000 0 0x1000>;
296		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
297			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
298		pcie@0 {
299			ranges = <0x02000000 0 0xe0000000
300				  0x02000000 0 0xe0000000
301				  0 0x20000000
302
303				  0x01000000 0 0x00000000
304				  0x01000000 0 0x00000000
305				  0 0x00010000>;
306		};
307	};
308
309	pci1: pcie@ffe201000 {
310		reg = <0xf 0xfe201000 0 0x1000>;
311		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
312			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
313		pcie@0 {
314			ranges = <0x02000000 0 0xe0000000
315				  0x02000000 0 0xe0000000
316				  0 0x20000000
317
318				  0x01000000 0 0x00000000
319				  0x01000000 0 0x00000000
320				  0 0x00010000>;
321		};
322	};
323
324	pci2: pcie@ffe202000 {
325		reg = <0xf 0xfe202000 0 0x1000>;
326		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
327			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
328		pcie@0 {
329			ranges = <0x02000000 0 0xe0000000
330				  0x02000000 0 0xe0000000
331				  0 0x20000000
332
333				  0x01000000 0 0x00000000
334				  0x01000000 0 0x00000000
335				  0 0x00010000>;
336		};
337	};
338};
339
340/include/ "p2041si-post.dtsi"
341