1/*
2 * P1025 RDB Device Tree Source (32-bit address map)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "p1021si-pre.dtsi"
36/ {
37	model = "fsl,P1025RDB";
38	compatible = "fsl,P1025RDB";
39
40	memory {
41		device_type = "memory";
42	};
43
44	lbc: localbus@ffe05000 {
45		reg = <0 0xffe05000 0 0x1000>;
46
47		/* NOR, NAND Flashes */
48		ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49			  0x1 0x0 0x0 0xff800000 0x00040000>;
50	};
51
52	soc: soc@ffe00000 {
53		ranges = <0x0 0x0 0xffe00000 0x100000>;
54	};
55
56	pci0: pcie@ffe09000 {
57		ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
58			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59		reg = <0 0xffe09000 0 0x1000>;
60		pcie@0 {
61			ranges = <0x2000000 0x0 0xe0000000
62				  0x2000000 0x0 0xe0000000
63				  0x0 0x20000000
64
65				  0x1000000 0x0 0x0
66				  0x1000000 0x0 0x0
67				  0x0 0x100000>;
68		};
69	};
70
71	pci1: pcie@ffe0a000 {
72		reg = <0 0xffe0a000 0 0x1000>;
73		ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
74			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
75		pcie@0 {
76			ranges = <0x2000000 0x0 0xe0000000
77				  0x2000000 0x0 0xe0000000
78				  0x0 0x20000000
79
80				  0x1000000 0x0 0x0
81				  0x1000000 0x0 0x0
82				  0x0 0x100000>;
83		};
84	};
85
86	qe: qe@ffe80000 {
87		ranges = <0x0 0x0 0xffe80000 0x40000>;
88		reg = <0 0xffe80000 0 0x480>;
89		brg-frequency = <0>;
90		bus-frequency = <0>;
91		status = "disabled"; /* no firmware loaded */
92
93		enet3: ucc@2000 {
94			device_type = "network";
95			compatible = "ucc_geth";
96			rx-clock-name = "clk12";
97			tx-clock-name = "clk9";
98			pio-handle = <&pio1>;
99			phy-handle = <&qe_phy0>;
100			phy-connection-type = "mii";
101		};
102
103		mdio@2120 {
104			qe_phy0: ethernet-phy@0 {
105				interrupt-parent = <&mpic>;
106				interrupts = <4 1 0 0>;
107				reg = <0x6>;
108			};
109			qe_phy1: ethernet-phy@3 {
110				interrupt-parent = <&mpic>;
111				interrupts = <5 1 0 0>;
112				reg = <0x3>;
113			};
114			tbi-phy@11 {
115				reg = <0x11>;
116				device_type = "tbi-phy";
117			};
118		};
119
120		enet4: ucc@2400 {
121			device_type = "network";
122			compatible = "ucc_geth";
123			rx-clock-name = "none";
124			tx-clock-name = "clk13";
125			pio-handle = <&pio2>;
126			phy-handle = <&qe_phy1>;
127			phy-connection-type = "rmii";
128		};
129	};
130};
131
132/include/ "p1025rdb.dtsi"
133/include/ "p1021si-post.dtsi"
134