1/*
2 * Cyrus 5020 Device Tree Source, based on p5020ds.dts
3 *
4 * Copyright 2015 Andy Fleming
5 *
6 * p5020ds.dts copyright:
7 * Copyright 2010 - 2014 Freescale Semiconductor Inc.
8 *
9 * This program is free software; you can redistribute  it and/or modify it
10 * under  the terms of  the GNU General  Public License as published by the
11 * Free Software Foundation;  either version 2 of the  License, or (at your
12 * option) any later version.
13 */
14
15/include/ "p5020si-pre.dtsi"
16
17/ {
18	model = "varisys,CYRUS";
19	compatible = "varisys,CYRUS";
20	#address-cells = <2>;
21	#size-cells = <2>;
22	interrupt-parent = <&mpic>;
23
24	memory {
25		device_type = "memory";
26	};
27
28	reserved-memory {
29		#address-cells = <2>;
30		#size-cells = <2>;
31		ranges;
32
33		bman_fbpr: bman-fbpr {
34			size = <0 0x1000000>;
35			alignment = <0 0x1000000>;
36		};
37		qman_fqd: qman-fqd {
38			size = <0 0x400000>;
39			alignment = <0 0x400000>;
40		};
41		qman_pfdr: qman-pfdr {
42			size = <0 0x2000000>;
43			alignment = <0 0x2000000>;
44		};
45	};
46
47	dcsr: dcsr@f00000000 {
48		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
49	};
50
51	bportals: bman-portals@ff4000000 {
52		ranges = <0x0 0xf 0xf4000000 0x200000>;
53	};
54
55	qportals: qman-portals@ff4200000 {
56		ranges = <0x0 0xf 0xf4200000 0x200000>;
57	};
58
59	soc: soc@ffe000000 {
60		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
61		reg = <0xf 0xfe000000 0 0x00001000>;
62		spi@110000 {
63		};
64
65		i2c@118100 {
66		};
67
68		i2c@119100 {
69			rtc@6f {
70				compatible = "microchip,mcp7941x";
71				reg = <0x6f>;
72			};
73		};
74	};
75
76	rio: rapidio@ffe0c0000 {
77		reg = <0xf 0xfe0c0000 0 0x11000>;
78
79		port1 {
80			ranges = <0 0 0xc 0x20000000 0 0x10000000>;
81		};
82		port2 {
83			ranges = <0 0 0xc 0x30000000 0 0x10000000>;
84		};
85	};
86
87	lbc: localbus@ffe124000 {
88		reg = <0xf 0xfe124000 0 0x1000>;
89		ranges = <0 0 0xf 0xe8000000 0x08000000
90			  2 0 0xf 0xffa00000 0x00040000
91			  3 0 0xf 0xffdf0000 0x00008000>;
92	};
93
94	pci0: pcie@ffe200000 {
95		reg = <0xf 0xfe200000 0 0x1000>;
96		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
97			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
98		pcie@0 {
99			ranges = <0x02000000 0 0xe0000000
100				  0x02000000 0 0xe0000000
101				  0 0x20000000
102
103				  0x01000000 0 0x00000000
104				  0x01000000 0 0x00000000
105				  0 0x00010000>;
106		};
107	};
108
109	pci1: pcie@ffe201000 {
110		reg = <0xf 0xfe201000 0 0x1000>;
111		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
112			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
113		pcie@0 {
114			ranges = <0x02000000 0 0xe0000000
115				  0x02000000 0 0xe0000000
116				  0 0x20000000
117
118				  0x01000000 0 0x00000000
119				  0x01000000 0 0x00000000
120				  0 0x00010000>;
121		};
122	};
123
124	pci2: pcie@ffe202000 {
125		reg = <0xf 0xfe202000 0 0x1000>;
126		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
127			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
128		pcie@0 {
129			ranges = <0x02000000 0 0xe0000000
130				  0x02000000 0 0xe0000000
131				  0 0x20000000
132
133				  0x01000000 0 0x00000000
134				  0x01000000 0 0x00000000
135				  0 0x00010000>;
136		};
137	};
138
139	pci3: pcie@ffe203000 {
140		reg = <0xf 0xfe203000 0 0x1000>;
141		ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
142			  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
143		pcie@0 {
144			ranges = <0x02000000 0 0xe0000000
145				  0x02000000 0 0xe0000000
146				  0 0x20000000
147
148				  0x01000000 0 0x00000000
149				  0x01000000 0 0x00000000
150				  0 0x00010000>;
151		};
152	};
153};
154
155/include/ "p5020si-post.dtsi"
156