1/*
2 * Digsy MTC board Device Tree Source
3 *
4 * Copyright (C) 2009 Semihalf
5 *
6 * Based on the CM5200 by M. Balakowicz
7 *
8 * This program is free software; you can redistribute  it and/or modify it
9 * under  the terms of  the GNU General  Public License as published by the
10 * Free Software Foundation;  either version 2 of the  License, or (at your
11 * option) any later version.
12 */
13
14/include/ "mpc5200b.dtsi"
15
16&gpt0 { gpio-controller; fsl,has-wdt; };
17&gpt1 { gpio-controller; };
18
19/ {
20	model = "intercontrol,digsy-mtc";
21	compatible = "intercontrol,digsy-mtc";
22
23	memory {
24		reg = <0x00000000 0x02000000>;	// 32MB
25	};
26
27	soc5200@f0000000 {
28		rtc@800 {
29			status = "disabled";
30		};
31
32		spi@f00 {
33			msp430@0 {
34				compatible = "spidev";
35				spi-max-frequency = <32000>;
36				reg = <0>;
37			};
38		};
39
40		psc@2000 {		// PSC1
41			status = "disabled";
42		};
43
44		psc@2200 {		// PSC2
45			status = "disabled";
46		};
47
48		psc@2400 {		// PSC3
49			status = "disabled";
50		};
51
52		psc@2600 {		// PSC4
53			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
54		};
55
56		psc@2800 {		// PSC5
57			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
58		};
59
60		psc@2c00 {		// PSC6
61			status = "disabled";
62		};
63
64		ethernet@3000 {
65			phy-handle = <&phy0>;
66		};
67
68		mdio@3000 {
69			phy0: ethernet-phy@0 {
70				reg = <0>;
71			};
72		};
73
74		i2c@3d00 {
75			eeprom@50 {
76				compatible = "at,24c08";
77				reg = <0x50>;
78			};
79
80			rtc@56 {
81				compatible = "mc,rv3029c2";
82				reg = <0x56>;
83			};
84
85			rtc@68 {
86				compatible = "dallas,ds1339";
87				reg = <0x68>;
88			};
89		};
90
91		i2c@3d40 {
92			status = "disabled";
93		};
94	};
95
96	pci@f0000d00 {
97		interrupt-map-mask = <0xf800 0 0 7>;
98		interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
99				 0xc000 0 0 2 &mpc5200_pic 0 0 3
100				 0xc000 0 0 3 &mpc5200_pic 0 0 3
101				 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
102		clock-frequency = <0>; // From boot loader
103		interrupts = <2 8 0 2 9 0 2 10 0>;
104		bus-range = <0 0>;
105		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
106			  0x02000000 0 0x90000000 0x90000000 0 0x10000000
107			  0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
108	};
109
110	localbus {
111		ranges = <0 0 0xff000000 0x1000000
112			  4 0 0x60000000 0x0001000>;
113
114		// 16-bit flash device at LocalPlus Bus CS0
115		flash@0,0 {
116			compatible = "cfi-flash";
117			reg = <0 0 0x1000000>;
118			bank-width = <2>;
119			device-width = <2>;
120			#size-cells = <1>;
121			#address-cells = <1>;
122
123			partition@0 {
124				label = "kernel";
125				reg = <0x0 0x00200000>;
126			};
127			partition@200000 {
128				label = "root";
129				reg = <0x00200000 0x00300000>;
130			};
131			partition@500000 {
132				label = "user";
133				reg = <0x00500000 0x00a00000>;
134			};
135			partition@f00000 {
136				label = "u-boot";
137				reg = <0x00f00000 0x100000>;
138			};
139		};
140
141		can@4,0 {
142			compatible = "nxp,sja1000";
143			reg = <4 0x000 0x80>;
144			nxp,external-clock-frequency = <24000000>;
145			interrupts = <1 2 3>; // Level-low
146		};
147
148		can@4,100 {
149			compatible = "nxp,sja1000";
150			reg = <4 0x100 0x80>;
151			nxp,external-clock-frequency = <24000000>;
152			interrupts = <1 2 3>;  // Level-low
153		};
154
155		serial@4,200 {
156			compatible = "nxp,sc28l92";
157			reg = <4 0x200 0x10>;
158			interrupts = <1 3 3>;
159		};
160	};
161};
162