1/* 2 * CM5200 board Device Tree Source 3 * 4 * Copyright (C) 2007 Semihalf 5 * Marian Balakowicz <m8@semihalf.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/dts-v1/; 14 15/ { 16 model = "schindler,cm5200"; 17 compatible = "schindler,cm5200"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 PowerPC,5200@0 { 26 device_type = "cpu"; 27 reg = <0>; 28 d-cache-line-size = <32>; 29 i-cache-line-size = <32>; 30 d-cache-size = <0x4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K 32 timebase-frequency = <0>; // from bootloader 33 bus-frequency = <0>; // from bootloader 34 clock-frequency = <0>; // from bootloader 35 }; 36 }; 37 38 memory { 39 device_type = "memory"; 40 reg = <0x00000000 0x04000000>; // 64MB 41 }; 42 43 soc5200@f0000000 { 44 #address-cells = <1>; 45 #size-cells = <1>; 46 compatible = "fsl,mpc5200b-immr"; 47 ranges = <0 0xf0000000 0x0000c000>; 48 reg = <0xf0000000 0x00000100>; 49 bus-frequency = <0>; // from bootloader 50 system-frequency = <0>; // from bootloader 51 52 cdm@200 { 53 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 54 reg = <0x200 0x38>; 55 }; 56 57 mpc5200_pic: interrupt-controller@500 { 58 // 5200 interrupts are encoded into two levels; 59 interrupt-controller; 60 #interrupt-cells = <3>; 61 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 62 reg = <0x500 0x80>; 63 }; 64 65 timer@600 { // General Purpose Timer 66 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 reg = <0x600 0x10>; 68 interrupts = <1 9 0>; 69 interrupt-parent = <&mpc5200_pic>; 70 fsl,has-wdt; 71 }; 72 73 timer@610 { // General Purpose Timer 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 75 reg = <0x610 0x10>; 76 interrupts = <1 10 0>; 77 interrupt-parent = <&mpc5200_pic>; 78 }; 79 80 timer@620 { // General Purpose Timer 81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 82 reg = <0x620 0x10>; 83 interrupts = <1 11 0>; 84 interrupt-parent = <&mpc5200_pic>; 85 }; 86 87 timer@630 { // General Purpose Timer 88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 89 reg = <0x630 0x10>; 90 interrupts = <1 12 0>; 91 interrupt-parent = <&mpc5200_pic>; 92 }; 93 94 timer@640 { // General Purpose Timer 95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 96 reg = <0x640 0x10>; 97 interrupts = <1 13 0>; 98 interrupt-parent = <&mpc5200_pic>; 99 }; 100 101 timer@650 { // General Purpose Timer 102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 103 reg = <0x650 0x10>; 104 interrupts = <1 14 0>; 105 interrupt-parent = <&mpc5200_pic>; 106 }; 107 108 timer@660 { // General Purpose Timer 109 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 110 reg = <0x660 0x10>; 111 interrupts = <1 15 0>; 112 interrupt-parent = <&mpc5200_pic>; 113 }; 114 115 timer@670 { // General Purpose Timer 116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 117 reg = <0x670 0x10>; 118 interrupts = <1 16 0>; 119 interrupt-parent = <&mpc5200_pic>; 120 }; 121 122 rtc@800 { // Real time clock 123 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 124 reg = <0x800 0x100>; 125 interrupts = <1 5 0 1 6 0>; 126 interrupt-parent = <&mpc5200_pic>; 127 }; 128 129 gpio@b00 { 130 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 131 reg = <0xb00 0x40>; 132 interrupts = <1 7 0>; 133 interrupt-parent = <&mpc5200_pic>; 134 }; 135 136 gpio@c00 { 137 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 138 reg = <0xc00 0x40>; 139 interrupts = <1 8 0 0 3 0>; 140 interrupt-parent = <&mpc5200_pic>; 141 }; 142 143 spi@f00 { 144 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 145 reg = <0xf00 0x20>; 146 interrupts = <2 13 0 2 14 0>; 147 interrupt-parent = <&mpc5200_pic>; 148 }; 149 150 usb@1000 { 151 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 152 reg = <0x1000 0xff>; 153 interrupts = <2 6 0>; 154 interrupt-parent = <&mpc5200_pic>; 155 }; 156 157 dma-controller@1200 { 158 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 159 reg = <0x1200 0x80>; 160 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 161 3 4 0 3 5 0 3 6 0 3 7 0 162 3 8 0 3 9 0 3 10 0 3 11 0 163 3 12 0 3 13 0 3 14 0 3 15 0>; 164 interrupt-parent = <&mpc5200_pic>; 165 }; 166 167 xlb@1f00 { 168 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 169 reg = <0x1f00 0x100>; 170 }; 171 172 serial@2000 { // PSC1 173 device_type = "serial"; 174 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 175 port-number = <0>; // Logical port assignment 176 reg = <0x2000 0x100>; 177 interrupts = <2 1 0>; 178 interrupt-parent = <&mpc5200_pic>; 179 }; 180 181 serial@2200 { // PSC2 182 device_type = "serial"; 183 compatible = "fsl,mpc5200-psc-uart"; 184 port-number = <1>; // Logical port assignment 185 reg = <0x2200 0x100>; 186 interrupts = <2 2 0>; 187 interrupt-parent = <&mpc5200_pic>; 188 }; 189 190 serial@2400 { // PSC3 191 device_type = "serial"; 192 compatible = "fsl,mpc5200-psc-uart"; 193 port-number = <2>; // Logical port assignment 194 reg = <0x2400 0x100>; 195 interrupts = <2 3 0>; 196 interrupt-parent = <&mpc5200_pic>; 197 }; 198 199 serial@2c00 { // PSC6 200 device_type = "serial"; 201 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 202 port-number = <5>; // Logical port assignment 203 reg = <0x2c00 0x100>; 204 interrupts = <2 4 0>; 205 interrupt-parent = <&mpc5200_pic>; 206 }; 207 208 ethernet@3000 { 209 device_type = "network"; 210 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 211 reg = <0x3000 0x400>; 212 local-mac-address = [ 00 00 00 00 00 00 ]; 213 interrupts = <2 5 0>; 214 interrupt-parent = <&mpc5200_pic>; 215 phy-handle = <&phy0>; 216 }; 217 218 mdio@3000 { 219 #address-cells = <1>; 220 #size-cells = <0>; 221 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 222 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 223 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 224 interrupt-parent = <&mpc5200_pic>; 225 226 phy0: ethernet-phy@0 { 227 device_type = "ethernet-phy"; 228 reg = <0>; 229 }; 230 }; 231 232 i2c@3d40 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 236 reg = <0x3d40 0x40>; 237 interrupts = <2 16 0>; 238 interrupt-parent = <&mpc5200_pic>; 239 fsl5200-clocking; 240 }; 241 242 sram@8000 { 243 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 244 reg = <0x8000 0x4000>; 245 }; 246 }; 247 248 lpb { 249 model = "fsl,lpb"; 250 compatible = "fsl,lpb"; 251 #address-cells = <2>; 252 #size-cells = <1>; 253 ranges = <0 0 0xfc000000 0x2000000>; 254 255 // 16-bit flash device at LocalPlus Bus CS0 256 flash@0,0 { 257 compatible = "cfi-flash"; 258 reg = <0 0 0x2000000>; 259 bank-width = <2>; 260 device-width = <2>; 261 #size-cells = <1>; 262 #address-cells = <1>; 263 }; 264 }; 265}; 266