18bc4a51dSStefan Roese/* 28bc4a51dSStefan Roese * Device Tree Source for AMCC Canyonlands (460EX) 38bc4a51dSStefan Roese * 488eeb72eSStefan Roese * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de> 58bc4a51dSStefan Roese * 68bc4a51dSStefan Roese * This file is licensed under the terms of the GNU General Public 78bc4a51dSStefan Roese * License version 2. This program is licensed "as is" without 88bc4a51dSStefan Roese * any warranty of any kind, whether express or implied. 98bc4a51dSStefan Roese */ 108bc4a51dSStefan Roese 1171f34979SDavid Gibson/dts-v1/; 1271f34979SDavid Gibson 138bc4a51dSStefan Roese/ { 148bc4a51dSStefan Roese #address-cells = <2>; 158bc4a51dSStefan Roese #size-cells = <1>; 168bc4a51dSStefan Roese model = "amcc,canyonlands"; 178bc4a51dSStefan Roese compatible = "amcc,canyonlands"; 1871f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 198bc4a51dSStefan Roese 208bc4a51dSStefan Roese aliases { 218bc4a51dSStefan Roese ethernet0 = &EMAC0; 228bc4a51dSStefan Roese ethernet1 = &EMAC1; 238bc4a51dSStefan Roese serial0 = &UART0; 248bc4a51dSStefan Roese serial1 = &UART1; 258bc4a51dSStefan Roese }; 268bc4a51dSStefan Roese 278bc4a51dSStefan Roese cpus { 288bc4a51dSStefan Roese #address-cells = <1>; 298bc4a51dSStefan Roese #size-cells = <0>; 308bc4a51dSStefan Roese 318bc4a51dSStefan Roese cpu@0 { 328bc4a51dSStefan Roese device_type = "cpu"; 338bc4a51dSStefan Roese model = "PowerPC,460EX"; 3471f34979SDavid Gibson reg = <0x00000000>; 358bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 368bc4a51dSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3771f34979SDavid Gibson i-cache-line-size = <32>; 3871f34979SDavid Gibson d-cache-line-size = <32>; 3971f34979SDavid Gibson i-cache-size = <32768>; 4071f34979SDavid Gibson d-cache-size = <32768>; 418bc4a51dSStefan Roese dcr-controller; 428bc4a51dSStefan Roese dcr-access-method = "native"; 43cd85400aSStefan Roese next-level-cache = <&L2C0>; 448bc4a51dSStefan Roese }; 458bc4a51dSStefan Roese }; 468bc4a51dSStefan Roese 478bc4a51dSStefan Roese memory { 488bc4a51dSStefan Roese device_type = "memory"; 4971f34979SDavid Gibson reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 508bc4a51dSStefan Roese }; 518bc4a51dSStefan Roese 528bc4a51dSStefan Roese UIC0: interrupt-controller0 { 538bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 548bc4a51dSStefan Roese interrupt-controller; 558bc4a51dSStefan Roese cell-index = <0>; 5671f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 578bc4a51dSStefan Roese #address-cells = <0>; 588bc4a51dSStefan Roese #size-cells = <0>; 598bc4a51dSStefan Roese #interrupt-cells = <2>; 608bc4a51dSStefan Roese }; 618bc4a51dSStefan Roese 628bc4a51dSStefan Roese UIC1: interrupt-controller1 { 638bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 648bc4a51dSStefan Roese interrupt-controller; 658bc4a51dSStefan Roese cell-index = <1>; 6671f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 678bc4a51dSStefan Roese #address-cells = <0>; 688bc4a51dSStefan Roese #size-cells = <0>; 698bc4a51dSStefan Roese #interrupt-cells = <2>; 7071f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 718bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 728bc4a51dSStefan Roese }; 738bc4a51dSStefan Roese 748bc4a51dSStefan Roese UIC2: interrupt-controller2 { 758bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 768bc4a51dSStefan Roese interrupt-controller; 778bc4a51dSStefan Roese cell-index = <2>; 7871f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 798bc4a51dSStefan Roese #address-cells = <0>; 808bc4a51dSStefan Roese #size-cells = <0>; 818bc4a51dSStefan Roese #interrupt-cells = <2>; 8271f34979SDavid Gibson interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 838bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 848bc4a51dSStefan Roese }; 858bc4a51dSStefan Roese 868bc4a51dSStefan Roese UIC3: interrupt-controller3 { 878bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 888bc4a51dSStefan Roese interrupt-controller; 898bc4a51dSStefan Roese cell-index = <3>; 9071f34979SDavid Gibson dcr-reg = <0x0f0 0x009>; 918bc4a51dSStefan Roese #address-cells = <0>; 928bc4a51dSStefan Roese #size-cells = <0>; 938bc4a51dSStefan Roese #interrupt-cells = <2>; 9471f34979SDavid Gibson interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 958bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 968bc4a51dSStefan Roese }; 978bc4a51dSStefan Roese 988bc4a51dSStefan Roese SDR0: sdr { 998bc4a51dSStefan Roese compatible = "ibm,sdr-460ex"; 10071f34979SDavid Gibson dcr-reg = <0x00e 0x002>; 1018bc4a51dSStefan Roese }; 1028bc4a51dSStefan Roese 1038bc4a51dSStefan Roese CPR0: cpr { 1048bc4a51dSStefan Roese compatible = "ibm,cpr-460ex"; 10571f34979SDavid Gibson dcr-reg = <0x00c 0x002>; 1068bc4a51dSStefan Roese }; 1078bc4a51dSStefan Roese 108ee2ffd8bSVictor Gallardo CPM0: cpm { 109ee2ffd8bSVictor Gallardo compatible = "ibm,cpm"; 110ee2ffd8bSVictor Gallardo dcr-access-method = "native"; 111ee2ffd8bSVictor Gallardo dcr-reg = <0x160 0x003>; 112ee2ffd8bSVictor Gallardo unused-units = <0x00000100>; 113ee2ffd8bSVictor Gallardo idle-doze = <0x02000000>; 114ee2ffd8bSVictor Gallardo standby = <0xfeff791d>; 115ee2ffd8bSVictor Gallardo }; 116ee2ffd8bSVictor Gallardo 117cd85400aSStefan Roese L2C0: l2c { 118cd85400aSStefan Roese compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; 119cd85400aSStefan Roese dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 120cd85400aSStefan Roese 0x030 0x008>; /* L2 cache DCR's */ 121cd85400aSStefan Roese cache-line-size = <32>; /* 32 bytes */ 122cd85400aSStefan Roese cache-size = <262144>; /* L2, 256K */ 123cd85400aSStefan Roese interrupt-parent = <&UIC1>; 124cd85400aSStefan Roese interrupts = <11 1>; 125cd85400aSStefan Roese }; 126cd85400aSStefan Roese 1278bc4a51dSStefan Roese plb { 1288bc4a51dSStefan Roese compatible = "ibm,plb-460ex", "ibm,plb4"; 1298bc4a51dSStefan Roese #address-cells = <2>; 1308bc4a51dSStefan Roese #size-cells = <1>; 1318bc4a51dSStefan Roese ranges; 1328bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1338bc4a51dSStefan Roese 1348bc4a51dSStefan Roese SDRAM0: sdram { 1358bc4a51dSStefan Roese compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; 13671f34979SDavid Gibson dcr-reg = <0x010 0x002>; 1378bc4a51dSStefan Roese }; 1388bc4a51dSStefan Roese 139049359d6SJames Hsiao CRYPTO: crypto@180000 { 140049359d6SJames Hsiao compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto"; 141049359d6SJames Hsiao reg = <4 0x00180000 0x80400>; 142049359d6SJames Hsiao interrupt-parent = <&UIC0>; 143049359d6SJames Hsiao interrupts = <0x1d 0x4>; 144049359d6SJames Hsiao }; 145049359d6SJames Hsiao 1468bc4a51dSStefan Roese MAL0: mcmal { 1478bc4a51dSStefan Roese compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 14871f34979SDavid Gibson dcr-reg = <0x180 0x062>; 1498bc4a51dSStefan Roese num-tx-chans = <2>; 15071f34979SDavid Gibson num-rx-chans = <16>; 1518bc4a51dSStefan Roese #address-cells = <0>; 1528bc4a51dSStefan Roese #size-cells = <0>; 1538bc4a51dSStefan Roese interrupt-parent = <&UIC2>; 15471f34979SDavid Gibson interrupts = < /*TXEOB*/ 0x6 0x4 15571f34979SDavid Gibson /*RXEOB*/ 0x7 0x4 15671f34979SDavid Gibson /*SERR*/ 0x3 0x4 15771f34979SDavid Gibson /*TXDE*/ 0x4 0x4 15871f34979SDavid Gibson /*RXDE*/ 0x5 0x4>; 1598bc4a51dSStefan Roese }; 1608bc4a51dSStefan Roese 161018f76ecSBenjamin Herrenschmidt USB0: ehci@bffd0400 { 162018f76ecSBenjamin Herrenschmidt compatible = "ibm,usb-ehci-460ex", "usb-ehci"; 163018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC2>; 164018f76ecSBenjamin Herrenschmidt interrupts = <0x1d 4>; 165018f76ecSBenjamin Herrenschmidt reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>; 166018f76ecSBenjamin Herrenschmidt }; 167018f76ecSBenjamin Herrenschmidt 168018f76ecSBenjamin Herrenschmidt USB1: usb@bffd0000 { 169018f76ecSBenjamin Herrenschmidt compatible = "ohci-le"; 170018f76ecSBenjamin Herrenschmidt reg = <4 0xbffd0000 0x60>; 171018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC2>; 172018f76ecSBenjamin Herrenschmidt interrupts = <0x1e 4>; 173018f76ecSBenjamin Herrenschmidt }; 174018f76ecSBenjamin Herrenschmidt 175c89b3458STirumala Marri USBOTG0: usbotg@bff80000 { 176c89b3458STirumala Marri compatible = "amcc,dwc-otg"; 177c89b3458STirumala Marri reg = <0x4 0xbff80000 0x10000>; 178c89b3458STirumala Marri interrupt-parent = <&USBOTG0>; 179c89b3458STirumala Marri #interrupt-cells = <1>; 180c89b3458STirumala Marri #address-cells = <0>; 181c89b3458STirumala Marri #size-cells = <0>; 182c89b3458STirumala Marri interrupts = <0x0 0x1 0x2>; 183c89b3458STirumala Marri interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4 184c89b3458STirumala Marri /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8 185c89b3458STirumala Marri /* DMA */ 0x2 &UIC0 0xc 0x4>; 186c89b3458STirumala Marri }; 187c89b3458STirumala Marri 18831fc0bd4SRupjyoti Sarmah SATA0: sata@bffd1000 { 18931fc0bd4SRupjyoti Sarmah compatible = "amcc,sata-460ex"; 19031fc0bd4SRupjyoti Sarmah reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>; 19131fc0bd4SRupjyoti Sarmah interrupt-parent = <&UIC3>; 19231fc0bd4SRupjyoti Sarmah interrupts = <0x0 0x4 /* SATA */ 19331fc0bd4SRupjyoti Sarmah 0x5 0x4>; /* AHBDMA */ 19431fc0bd4SRupjyoti Sarmah }; 19531fc0bd4SRupjyoti Sarmah 1968bc4a51dSStefan Roese POB0: opb { 1978bc4a51dSStefan Roese compatible = "ibm,opb-460ex", "ibm,opb"; 1988bc4a51dSStefan Roese #address-cells = <1>; 1998bc4a51dSStefan Roese #size-cells = <1>; 20071f34979SDavid Gibson ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 2018bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2028bc4a51dSStefan Roese 2038bc4a51dSStefan Roese EBC0: ebc { 2048bc4a51dSStefan Roese compatible = "ibm,ebc-460ex", "ibm,ebc"; 20571f34979SDavid Gibson dcr-reg = <0x012 0x002>; 2068bc4a51dSStefan Roese #address-cells = <2>; 2078bc4a51dSStefan Roese #size-cells = <1>; 2088bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2095020231bSStefan Roese /* ranges property is supplied by U-Boot */ 21071f34979SDavid Gibson interrupts = <0x6 0x4>; 2118bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 2125020231bSStefan Roese 2135020231bSStefan Roese nor_flash@0,0 { 2145020231bSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 2155020231bSStefan Roese bank-width = <2>; 21671f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 2175020231bSStefan Roese #address-cells = <1>; 2185020231bSStefan Roese #size-cells = <1>; 2195020231bSStefan Roese partition@0 { 2205020231bSStefan Roese label = "kernel"; 22171f34979SDavid Gibson reg = <0x00000000 0x001e0000>; 2225020231bSStefan Roese }; 2235020231bSStefan Roese partition@1e0000 { 2245020231bSStefan Roese label = "dtb"; 22571f34979SDavid Gibson reg = <0x001e0000 0x00020000>; 2265020231bSStefan Roese }; 2275020231bSStefan Roese partition@200000 { 2285020231bSStefan Roese label = "ramdisk"; 22971f34979SDavid Gibson reg = <0x00200000 0x01400000>; 2305020231bSStefan Roese }; 2315020231bSStefan Roese partition@1600000 { 2325020231bSStefan Roese label = "jffs2"; 23371f34979SDavid Gibson reg = <0x01600000 0x00400000>; 2345020231bSStefan Roese }; 2355020231bSStefan Roese partition@1a00000 { 2365020231bSStefan Roese label = "user"; 23771f34979SDavid Gibson reg = <0x01a00000 0x02560000>; 2385020231bSStefan Roese }; 2395020231bSStefan Roese partition@3f60000 { 2405020231bSStefan Roese label = "env"; 24171f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 2425020231bSStefan Roese }; 2435020231bSStefan Roese partition@3fa0000 { 2445020231bSStefan Roese label = "u-boot"; 24571f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 2465020231bSStefan Roese }; 2475020231bSStefan Roese }; 24888eeb72eSStefan Roese 2498960f7ffSRupjyoti Sarmah cpld@2,0 { 2508960f7ffSRupjyoti Sarmah compatible = "amcc,ppc460ex-bcsr"; 2518960f7ffSRupjyoti Sarmah reg = <2 0x0 0x9>; 2528960f7ffSRupjyoti Sarmah }; 2538960f7ffSRupjyoti Sarmah 25488eeb72eSStefan Roese ndfc@3,0 { 25588eeb72eSStefan Roese compatible = "ibm,ndfc"; 25688eeb72eSStefan Roese reg = <0x00000003 0x00000000 0x00002000>; 25788eeb72eSStefan Roese ccr = <0x00001000>; 25888eeb72eSStefan Roese bank-settings = <0x80002222>; 25988eeb72eSStefan Roese #address-cells = <1>; 26088eeb72eSStefan Roese #size-cells = <1>; 26188eeb72eSStefan Roese 26288eeb72eSStefan Roese nand { 26388eeb72eSStefan Roese #address-cells = <1>; 26488eeb72eSStefan Roese #size-cells = <1>; 26588eeb72eSStefan Roese 26688eeb72eSStefan Roese partition@0 { 26788eeb72eSStefan Roese label = "u-boot"; 26888eeb72eSStefan Roese reg = <0x00000000 0x00100000>; 26988eeb72eSStefan Roese }; 27088eeb72eSStefan Roese partition@100000 { 27188eeb72eSStefan Roese label = "user"; 27288eeb72eSStefan Roese reg = <0x00000000 0x03f00000>; 27388eeb72eSStefan Roese }; 27488eeb72eSStefan Roese }; 27588eeb72eSStefan Roese }; 2768bc4a51dSStefan Roese }; 2778bc4a51dSStefan Roese 2788bc4a51dSStefan Roese UART0: serial@ef600300 { 2798bc4a51dSStefan Roese device_type = "serial"; 2808bc4a51dSStefan Roese compatible = "ns16550"; 28171f34979SDavid Gibson reg = <0xef600300 0x00000008>; 28271f34979SDavid Gibson virtual-reg = <0xef600300>; 2838bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2848bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2858bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 28671f34979SDavid Gibson interrupts = <0x1 0x4>; 2878bc4a51dSStefan Roese }; 2888bc4a51dSStefan Roese 2898bc4a51dSStefan Roese UART1: serial@ef600400 { 2908bc4a51dSStefan Roese device_type = "serial"; 2918bc4a51dSStefan Roese compatible = "ns16550"; 29271f34979SDavid Gibson reg = <0xef600400 0x00000008>; 29371f34979SDavid Gibson virtual-reg = <0xef600400>; 2948bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2958bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2968bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 29771f34979SDavid Gibson interrupts = <0x1 0x4>; 2988bc4a51dSStefan Roese }; 2998bc4a51dSStefan Roese 3008bc4a51dSStefan Roese IIC0: i2c@ef600700 { 3018bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 30271f34979SDavid Gibson reg = <0xef600700 0x00000014>; 3038bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 30471f34979SDavid Gibson interrupts = <0x2 0x4>; 305018f76ecSBenjamin Herrenschmidt #address-cells = <1>; 306018f76ecSBenjamin Herrenschmidt #size-cells = <0>; 307018f76ecSBenjamin Herrenschmidt rtc@68 { 308018f76ecSBenjamin Herrenschmidt compatible = "stm,m41t80"; 309018f76ecSBenjamin Herrenschmidt reg = <0x68>; 310018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC2>; 311018f76ecSBenjamin Herrenschmidt interrupts = <0x19 0x8>; 312018f76ecSBenjamin Herrenschmidt }; 313018f76ecSBenjamin Herrenschmidt sttm@48 { 314018f76ecSBenjamin Herrenschmidt compatible = "ad,ad7414"; 315018f76ecSBenjamin Herrenschmidt reg = <0x48>; 316018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC1>; 317018f76ecSBenjamin Herrenschmidt interrupts = <0x14 0x8>; 318018f76ecSBenjamin Herrenschmidt }; 3198bc4a51dSStefan Roese }; 3208bc4a51dSStefan Roese 3218bc4a51dSStefan Roese IIC1: i2c@ef600800 { 3228bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 32371f34979SDavid Gibson reg = <0xef600800 0x00000014>; 3248bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 32571f34979SDavid Gibson interrupts = <0x3 0x4>; 3268bc4a51dSStefan Roese }; 3278bc4a51dSStefan Roese 3288960f7ffSRupjyoti Sarmah GPIO0: gpio@ef600b00 { 3298960f7ffSRupjyoti Sarmah compatible = "ibm,ppc4xx-gpio"; 3308960f7ffSRupjyoti Sarmah reg = <0xef600b00 0x00000048>; 3318960f7ffSRupjyoti Sarmah gpio-controller; 3328960f7ffSRupjyoti Sarmah }; 3338960f7ffSRupjyoti Sarmah 3348bc4a51dSStefan Roese ZMII0: emac-zmii@ef600d00 { 3358bc4a51dSStefan Roese compatible = "ibm,zmii-460ex", "ibm,zmii"; 33671f34979SDavid Gibson reg = <0xef600d00 0x0000000c>; 3378bc4a51dSStefan Roese }; 3388bc4a51dSStefan Roese 3398bc4a51dSStefan Roese RGMII0: emac-rgmii@ef601500 { 3408bc4a51dSStefan Roese compatible = "ibm,rgmii-460ex", "ibm,rgmii"; 34171f34979SDavid Gibson reg = <0xef601500 0x00000008>; 3428bc4a51dSStefan Roese has-mdio; 3438bc4a51dSStefan Roese }; 3448bc4a51dSStefan Roese 345a6190a84SStefan Roese TAH0: emac-tah@ef601350 { 346a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 34771f34979SDavid Gibson reg = <0xef601350 0x00000030>; 348a6190a84SStefan Roese }; 349a6190a84SStefan Roese 350a6190a84SStefan Roese TAH1: emac-tah@ef601450 { 351a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 35271f34979SDavid Gibson reg = <0xef601450 0x00000030>; 353a6190a84SStefan Roese }; 354a6190a84SStefan Roese 3558bc4a51dSStefan Roese EMAC0: ethernet@ef600e00 { 3568bc4a51dSStefan Roese device_type = "network"; 35705781ccdSGrant Erickson compatible = "ibm,emac-460ex", "ibm,emac4sync"; 3588bc4a51dSStefan Roese interrupt-parent = <&EMAC0>; 35971f34979SDavid Gibson interrupts = <0x0 0x1>; 3608bc4a51dSStefan Roese #interrupt-cells = <1>; 3618bc4a51dSStefan Roese #address-cells = <0>; 3628bc4a51dSStefan Roese #size-cells = <0>; 36371f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 36471f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x14 0x4>; 36505781ccdSGrant Erickson reg = <0xef600e00 0x000000c4>; 3668bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 3678bc4a51dSStefan Roese mal-device = <&MAL0>; 3688bc4a51dSStefan Roese mal-tx-channel = <0>; 3698bc4a51dSStefan Roese mal-rx-channel = <0>; 3708bc4a51dSStefan Roese cell-index = <0>; 37171f34979SDavid Gibson max-frame-size = <9000>; 37271f34979SDavid Gibson rx-fifo-size = <4096>; 37371f34979SDavid Gibson tx-fifo-size = <2048>; 374835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 3758bc4a51dSStefan Roese phy-mode = "rgmii"; 37671f34979SDavid Gibson phy-map = <0x00000000>; 3778bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 3788bc4a51dSStefan Roese rgmii-channel = <0>; 379a6190a84SStefan Roese tah-device = <&TAH0>; 380a6190a84SStefan Roese tah-channel = <0>; 3818bc4a51dSStefan Roese has-inverted-stacr-oc; 3828bc4a51dSStefan Roese has-new-stacr-staopc; 3838bc4a51dSStefan Roese }; 3848bc4a51dSStefan Roese 3858bc4a51dSStefan Roese EMAC1: ethernet@ef600f00 { 3868bc4a51dSStefan Roese device_type = "network"; 38705781ccdSGrant Erickson compatible = "ibm,emac-460ex", "ibm,emac4sync"; 3888bc4a51dSStefan Roese interrupt-parent = <&EMAC1>; 38971f34979SDavid Gibson interrupts = <0x0 0x1>; 3908bc4a51dSStefan Roese #interrupt-cells = <1>; 3918bc4a51dSStefan Roese #address-cells = <0>; 3928bc4a51dSStefan Roese #size-cells = <0>; 39371f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 39471f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x15 0x4>; 39505781ccdSGrant Erickson reg = <0xef600f00 0x000000c4>; 3968bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 3978bc4a51dSStefan Roese mal-device = <&MAL0>; 3988bc4a51dSStefan Roese mal-tx-channel = <1>; 3998bc4a51dSStefan Roese mal-rx-channel = <8>; 4008bc4a51dSStefan Roese cell-index = <1>; 40171f34979SDavid Gibson max-frame-size = <9000>; 40271f34979SDavid Gibson rx-fifo-size = <4096>; 40371f34979SDavid Gibson tx-fifo-size = <2048>; 404835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 4058bc4a51dSStefan Roese phy-mode = "rgmii"; 40671f34979SDavid Gibson phy-map = <0x00000000>; 4078bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 4088bc4a51dSStefan Roese rgmii-channel = <1>; 409a6190a84SStefan Roese tah-device = <&TAH1>; 410a6190a84SStefan Roese tah-channel = <1>; 4118bc4a51dSStefan Roese has-inverted-stacr-oc; 4128bc4a51dSStefan Roese has-new-stacr-staopc; 413a6190a84SStefan Roese mdio-device = <&EMAC0>; 4148bc4a51dSStefan Roese }; 4158bc4a51dSStefan Roese }; 4168bc4a51dSStefan Roese 4178bc4a51dSStefan Roese PCIX0: pci@c0ec00000 { 4188bc4a51dSStefan Roese device_type = "pci"; 4198bc4a51dSStefan Roese #interrupt-cells = <1>; 4208bc4a51dSStefan Roese #size-cells = <2>; 4218bc4a51dSStefan Roese #address-cells = <3>; 4228bc4a51dSStefan Roese compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; 4238bc4a51dSStefan Roese primary; 4248bc4a51dSStefan Roese large-inbound-windows; 4258bc4a51dSStefan Roese enable-msi-hole; 42671f34979SDavid Gibson reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 42771f34979SDavid Gibson 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 42871f34979SDavid Gibson 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 42971f34979SDavid Gibson 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 43071f34979SDavid Gibson 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 4318bc4a51dSStefan Roese 4328bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 4338bc4a51dSStefan Roese * later cannot be changed 4348bc4a51dSStefan Roese */ 43571f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 43684d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 43771f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 4388bc4a51dSStefan Roese 4398bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 44071f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 4418bc4a51dSStefan Roese 4428bc4a51dSStefan Roese /* This drives busses 0 to 0x3f */ 44371f34979SDavid Gibson bus-range = <0x0 0x3f>; 4448bc4a51dSStefan Roese 4458bc4a51dSStefan Roese /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 44671f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x0>; 44771f34979SDavid Gibson interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; 4488bc4a51dSStefan Roese }; 4498bc4a51dSStefan Roese 4508bc4a51dSStefan Roese PCIE0: pciex@d00000000 { 4518bc4a51dSStefan Roese device_type = "pci"; 4528bc4a51dSStefan Roese #interrupt-cells = <1>; 4538bc4a51dSStefan Roese #size-cells = <2>; 4548bc4a51dSStefan Roese #address-cells = <3>; 4558bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 4568bc4a51dSStefan Roese primary; 45771f34979SDavid Gibson port = <0x0>; /* port number */ 45871f34979SDavid Gibson reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 45971f34979SDavid Gibson 0x0000000c 0x08010000 0x00001000>; /* Registers */ 46071f34979SDavid Gibson dcr-reg = <0x100 0x020>; 46171f34979SDavid Gibson sdr-base = <0x300>; 4628bc4a51dSStefan Roese 4638bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 4648bc4a51dSStefan Roese * later cannot be changed 4658bc4a51dSStefan Roese */ 46671f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 46784d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 46871f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 4698bc4a51dSStefan Roese 4708bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 47171f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 4728bc4a51dSStefan Roese 4738bc4a51dSStefan Roese /* This drives busses 40 to 0x7f */ 47471f34979SDavid Gibson bus-range = <0x40 0x7f>; 4758bc4a51dSStefan Roese 4768bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 4778bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 4788bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 4798bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 4808bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 4818bc4a51dSStefan Roese * below are basically de-swizzled numbers. 4828bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 4838bc4a51dSStefan Roese */ 48471f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4858bc4a51dSStefan Roese interrupt-map = < 48671f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ 48771f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ 48871f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ 48971f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; 4908bc4a51dSStefan Roese }; 4918bc4a51dSStefan Roese 4928bc4a51dSStefan Roese PCIE1: pciex@d20000000 { 4938bc4a51dSStefan Roese device_type = "pci"; 4948bc4a51dSStefan Roese #interrupt-cells = <1>; 4958bc4a51dSStefan Roese #size-cells = <2>; 4968bc4a51dSStefan Roese #address-cells = <3>; 4978bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 4988bc4a51dSStefan Roese primary; 49971f34979SDavid Gibson port = <0x1>; /* port number */ 50071f34979SDavid Gibson reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 50171f34979SDavid Gibson 0x0000000c 0x08011000 0x00001000>; /* Registers */ 50271f34979SDavid Gibson dcr-reg = <0x120 0x020>; 50371f34979SDavid Gibson sdr-base = <0x340>; 5048bc4a51dSStefan Roese 5058bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 5068bc4a51dSStefan Roese * later cannot be changed 5078bc4a51dSStefan Roese */ 50871f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 50984d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 51071f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 5118bc4a51dSStefan Roese 5128bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 51371f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 5148bc4a51dSStefan Roese 5158bc4a51dSStefan Roese /* This drives busses 80 to 0xbf */ 51671f34979SDavid Gibson bus-range = <0x80 0xbf>; 5178bc4a51dSStefan Roese 5188bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 5198bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 5208bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 5218bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 5228bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 5238bc4a51dSStefan Roese * below are basically de-swizzled numbers. 5248bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 5258bc4a51dSStefan Roese */ 52671f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 5278bc4a51dSStefan Roese interrupt-map = < 52871f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ 52971f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ 53071f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ 53171f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; 5328bc4a51dSStefan Roese }; 5338bc4a51dSStefan Roese }; 5348bc4a51dSStefan Roese}; 535