1/*
2 * Device Tree for Bluestone (APM821xx) board.
3 *
4 * Copyright (c) 2010, Applied Micro Circuits Corporation
5 * Author: Tirumala R Marri <tmarri@apm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24/dts-v1/;
25
26/ {
27	#address-cells = <2>;
28	#size-cells = <1>;
29	model = "apm,bluestone";
30	compatible = "apm,bluestone";
31	dcr-parent = <&{/cpus/cpu@0}>;
32
33	aliases {
34		ethernet0 = &EMAC0;
35		serial0 = &UART0;
36		serial1 = &UART1;
37	};
38
39	cpus {
40		#address-cells = <1>;
41		#size-cells = <0>;
42
43		cpu@0 {
44			device_type = "cpu";
45			model = "PowerPC,apm821xx";
46			reg = <0x00000000>;
47			clock-frequency = <0>; /* Filled in by U-Boot */
48			timebase-frequency = <0>; /* Filled in by U-Boot */
49			i-cache-line-size = <32>;
50			d-cache-line-size = <32>;
51			i-cache-size = <32768>;
52			d-cache-size = <32768>;
53			dcr-controller;
54			dcr-access-method = "native";
55			next-level-cache = <&L2C0>;
56		};
57	};
58
59	memory {
60		device_type = "memory";
61		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
62	};
63
64	UIC0: interrupt-controller0 {
65		compatible = "ibm,uic";
66		interrupt-controller;
67		cell-index = <0>;
68		dcr-reg = <0x0c0 0x009>;
69		#address-cells = <0>;
70		#size-cells = <0>;
71		#interrupt-cells = <2>;
72	};
73
74	UIC1: interrupt-controller1 {
75		compatible = "ibm,uic";
76		interrupt-controller;
77		cell-index = <1>;
78		dcr-reg = <0x0d0 0x009>;
79		#address-cells = <0>;
80		#size-cells = <0>;
81		#interrupt-cells = <2>;
82		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
83		interrupt-parent = <&UIC0>;
84	};
85
86	UIC2: interrupt-controller2 {
87		compatible = "ibm,uic";
88		interrupt-controller;
89		cell-index = <2>;
90		dcr-reg = <0x0e0 0x009>;
91		#address-cells = <0>;
92		#size-cells = <0>;
93		#interrupt-cells = <2>;
94		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
95		interrupt-parent = <&UIC0>;
96	};
97
98	UIC3: interrupt-controller3 {
99		compatible = "ibm,uic";
100		interrupt-controller;
101		cell-index = <3>;
102		dcr-reg = <0x0f0 0x009>;
103		#address-cells = <0>;
104		#size-cells = <0>;
105		#interrupt-cells = <2>;
106		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
107		interrupt-parent = <&UIC0>;
108	};
109
110	SDR0: sdr {
111		compatible = "ibm,sdr-apm821xx";
112		dcr-reg = <0x00e 0x002>;
113	};
114
115	CPR0: cpr {
116		compatible = "ibm,cpr-apm821xx";
117		dcr-reg = <0x00c 0x002>;
118	};
119
120	L2C0: l2c {
121		compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
122		dcr-reg = <0x020 0x008
123			   0x030 0x008>;
124		cache-line-size = <32>;
125		cache-size = <262144>;
126		interrupt-parent = <&UIC1>;
127		interrupts = <11 1>;
128	};
129
130	plb {
131		compatible = "ibm,plb4";
132		#address-cells = <2>;
133		#size-cells = <1>;
134		ranges;
135		clock-frequency = <0>; /* Filled in by U-Boot */
136
137		SDRAM0: sdram {
138			compatible = "ibm,sdram-apm821xx";
139			dcr-reg = <0x010 0x002>;
140		};
141
142		MAL0: mcmal {
143			compatible = "ibm,mcmal2";
144			descriptor-memory = "ocm";
145			dcr-reg = <0x180 0x062>;
146			num-tx-chans = <1>;
147			num-rx-chans = <1>;
148			#address-cells = <0>;
149			#size-cells = <0>;
150			interrupt-parent = <&UIC2>;
151			interrupts = <	/*TXEOB*/ 0x6 0x4
152					/*RXEOB*/ 0x7 0x4
153					/*SERR*/  0x3 0x4
154					/*TXDE*/  0x4 0x4
155					/*RXDE*/  0x5 0x4>;
156		};
157
158		POB0: opb {
159			compatible = "ibm,opb";
160			#address-cells = <1>;
161			#size-cells = <1>;
162			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
163			clock-frequency = <0>; /* Filled in by U-Boot */
164
165			EBC0: ebc {
166				compatible = "ibm,ebc";
167				dcr-reg = <0x012 0x002>;
168				#address-cells = <2>;
169				#size-cells = <1>;
170				clock-frequency = <0>; /* Filled in by U-Boot */
171				/* ranges property is supplied by U-Boot */
172				ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
173				interrupts = <0x6 0x4>;
174				interrupt-parent = <&UIC1>;
175
176				nor_flash@0,0 {
177					compatible = "amd,s29gl512n", "cfi-flash";
178					bank-width = <2>;
179					reg = <0x00000000 0x00000000 0x00400000>;
180					#address-cells = <1>;
181					#size-cells = <1>;
182					partition@0 {
183						label = "kernel";
184						reg = <0x00000000 0x00180000>;
185					};
186					partition@180000 {
187						label = "env";
188						reg = <0x00180000 0x00020000>;
189					};
190					partition@1a0000 {
191						label = "u-boot";
192						reg = <0x001a0000 0x00060000>;
193					};
194				};
195
196				ndfc@1,0 {
197					compatible = "ibm,ndfc";
198					reg = <0x00000003 0x00000000 0x00002000>;
199					ccr = <0x00001000>;
200					bank-settings = <0x80002222>;
201					#address-cells = <1>;
202					#size-cells = <1>;
203					/* 2Gb Nand Flash */
204					nand {
205						#address-cells = <1>;
206						#size-cells = <1>;
207
208						partition@0 {
209							label = "firmware";
210							reg   = <0x00000000 0x00C00000>;
211						};
212						partition@c00000 {
213							label = "environment";
214							reg   = <0x00C00000 0x00B00000>;
215						};
216						partition@1700000 {
217							label = "kernel";
218							reg   = <0x01700000 0x00E00000>;
219						};
220						partition@2500000 {
221							label = "root";
222							reg   = <0x02500000 0x08200000>;
223						};
224						partition@a700000 {
225							label = "device-tree";
226							reg   = <0x0A700000 0x00B00000>;
227						};
228						partition@b200000 {
229							label = "config";
230							reg   = <0x0B200000 0x00D00000>;
231						};
232						partition@bf00000 {
233							label = "diag";
234							reg   = <0x0BF00000 0x00C00000>;
235						};
236						partition@cb00000 {
237							label = "vendor";
238							reg   = <0x0CB00000 0x3500000>;
239						};
240					};
241				};
242			};
243
244			UART0: serial@ef600300 {
245				device_type = "serial";
246				compatible = "ns16550";
247				reg = <0xef600300 0x00000008>;
248				virtual-reg = <0xef600300>;
249				clock-frequency = <0>; /* Filled in by U-Boot */
250				current-speed = <0>; /* Filled in by U-Boot */
251				interrupt-parent = <&UIC1>;
252				interrupts = <0x1 0x4>;
253			};
254
255			UART1: serial@ef600400 {
256				device_type = "serial";
257				compatible = "ns16550";
258				reg = <0xef600400 0x00000008>;
259				virtual-reg = <0xef600400>;
260				clock-frequency = <0>; /* Filled in by U-Boot */
261				current-speed = <0>; /* Filled in by U-Boot */
262				interrupt-parent = <&UIC0>;
263				interrupts = <0x1 0x4>;
264			};
265
266			IIC0: i2c@ef600700 {
267				compatible = "ibm,iic";
268				reg = <0xef600700 0x00000014>;
269				interrupt-parent = <&UIC0>;
270				interrupts = <0x2 0x4>;
271				#address-cells = <1>;
272				#size-cells = <0>;
273				rtc@68 {
274					compatible = "stm,m41t80";
275					reg = <0x68>;
276					interrupt-parent = <&UIC0>;
277					interrupts = <0x9 0x8>;
278				};
279				sttm@4C {
280					compatible = "adm,adm1032";
281					reg = <0x4C>;
282					interrupt-parent = <&UIC1>;
283					interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
284				};
285			};
286
287			IIC1: i2c@ef600800 {
288				compatible = "ibm,iic";
289				reg = <0xef600800 0x00000014>;
290				interrupt-parent = <&UIC0>;
291				interrupts = <0x3 0x4>;
292			};
293
294			RGMII0: emac-rgmii@ef601500 {
295				compatible = "ibm,rgmii";
296				reg = <0xef601500 0x00000008>;
297				has-mdio;
298			};
299
300			TAH0: emac-tah@ef601350 {
301				compatible = "ibm,tah";
302				reg = <0xef601350 0x00000030>;
303			};
304
305			EMAC0: ethernet@ef600c00 {
306				device_type = "network";
307				compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
308				interrupt-parent = <&EMAC0>;
309				interrupts = <0x0 0x1>;
310				#interrupt-cells = <1>;
311				#address-cells = <0>;
312				#size-cells = <0>;
313				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
314						 /*Wake*/   0x1 &UIC2 0x14 0x4>;
315				reg = <0xef600c00 0x000000c4>;
316				local-mac-address = [000000000000]; /* Filled in by U-Boot */
317				mal-device = <&MAL0>;
318				mal-tx-channel = <0>;
319				mal-rx-channel = <0>;
320				cell-index = <0>;
321				max-frame-size = <9000>;
322				rx-fifo-size = <16384>;
323				tx-fifo-size = <2048>;
324				phy-mode = "rgmii";
325				phy-map = <0x00000000>;
326				rgmii-device = <&RGMII0>;
327				rgmii-channel = <0>;
328				tah-device = <&TAH0>;
329				tah-channel = <0>;
330				has-inverted-stacr-oc;
331				has-new-stacr-staopc;
332			};
333		};
334
335		PCIE0: pciex@d00000000 {
336			device_type = "pci";
337			#interrupt-cells = <1>;
338			#size-cells = <2>;
339			#address-cells = <3>;
340			compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
341			primary;
342			port = <0x0>; /* port number */
343			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
344			       0x0000000c 0x08010000 0x00001000>;	/* Registers */
345			dcr-reg = <0x100 0x020>;
346			sdr-base = <0x300>;
347
348			/* Outbound ranges, one memory and one IO,
349			 * later cannot be changed
350			 */
351			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
352				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
353				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
354
355			/* Inbound 2GB range starting at 0 */
356			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
357
358			/* This drives busses 40 to 0x7f */
359			bus-range = <0x40 0x7f>;
360
361			/* Legacy interrupts (note the weird polarity, the bridge seems
362			 * to invert PCIe legacy interrupts).
363			 * We are de-swizzling here because the numbers are actually for
364			 * port of the root complex virtual P2P bridge. But I want
365			 * to avoid putting a node for it in the tree, so the numbers
366			 * below are basically de-swizzled numbers.
367			 * The real slot is on idsel 0, so the swizzling is 1:1
368			 */
369			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
370			interrupt-map = <
371				0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
372				0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
373				0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
374				0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
375		};
376
377		MSI: ppc4xx-msi@C10000000 {
378			compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
379			reg = < 0xC 0x10000000 0x100
380				0xC 0x10000000 0x100>;
381			sdr-base = <0x36C>;
382			msi-data = <0x00004440>;
383			msi-mask = <0x0000ffe0>;
384			interrupts =<0 1 2 3 4 5 6 7>;
385			interrupt-parent = <&MSI>;
386			#interrupt-cells = <1>;
387			#address-cells = <0>;
388			#size-cells = <0>;
389			msi-available-ranges = <0x0 0x100>;
390			interrupt-map = <
391				0 &UIC3 0x18 1
392				1 &UIC3 0x19 1
393				2 &UIC3 0x1A 1
394				3 &UIC3 0x1B 1
395				4 &UIC3 0x1C 1
396				5 &UIC3 0x1D 1
397				6 &UIC3 0x1E 1
398				7 &UIC3 0x1F 1
399			>;
400		};
401	};
402};
403