1/* 2 * Device Tree Source for AMCC Arches (dual 460GT board) 3 * 4 * (C) Copyright 2008 Applied Micro Circuits Corporation 5 * Victor Gallardo <vgallardo@amcc.com> 6 * Adam Graham <agraham@amcc.com> 7 * 8 * Based on the glacier.dts file 9 * Stefan Roese <sr@denx.de> 10 * Copyright 2008 DENX Software Engineering 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31/dts-v1/; 32 33/ { 34 #address-cells = <2>; 35 #size-cells = <1>; 36 model = "amcc,arches"; 37 compatible = "amcc,arches"; 38 dcr-parent = <&{/cpus/cpu@0}>; 39 40 aliases { 41 ethernet0 = &EMAC0; 42 ethernet1 = &EMAC1; 43 ethernet2 = &EMAC2; 44 serial0 = &UART0; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 cpu@0 { 52 device_type = "cpu"; 53 model = "PowerPC,460GT"; 54 reg = <0x00000000>; 55 clock-frequency = <0>; /* Filled in by U-Boot */ 56 timebase-frequency = <0>; /* Filled in by U-Boot */ 57 i-cache-line-size = <32>; 58 d-cache-line-size = <32>; 59 i-cache-size = <32768>; 60 d-cache-size = <32768>; 61 dcr-controller; 62 dcr-access-method = "native"; 63 next-level-cache = <&L2C0>; 64 }; 65 }; 66 67 memory { 68 device_type = "memory"; 69 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 70 }; 71 72 UIC0: interrupt-controller0 { 73 compatible = "ibm,uic-460gt","ibm,uic"; 74 interrupt-controller; 75 cell-index = <0>; 76 dcr-reg = <0x0c0 0x009>; 77 #address-cells = <0>; 78 #size-cells = <0>; 79 #interrupt-cells = <2>; 80 }; 81 82 UIC1: interrupt-controller1 { 83 compatible = "ibm,uic-460gt","ibm,uic"; 84 interrupt-controller; 85 cell-index = <1>; 86 dcr-reg = <0x0d0 0x009>; 87 #address-cells = <0>; 88 #size-cells = <0>; 89 #interrupt-cells = <2>; 90 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 91 interrupt-parent = <&UIC0>; 92 }; 93 94 UIC2: interrupt-controller2 { 95 compatible = "ibm,uic-460gt","ibm,uic"; 96 interrupt-controller; 97 cell-index = <2>; 98 dcr-reg = <0x0e0 0x009>; 99 #address-cells = <0>; 100 #size-cells = <0>; 101 #interrupt-cells = <2>; 102 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 103 interrupt-parent = <&UIC0>; 104 }; 105 106 UIC3: interrupt-controller3 { 107 compatible = "ibm,uic-460gt","ibm,uic"; 108 interrupt-controller; 109 cell-index = <3>; 110 dcr-reg = <0x0f0 0x009>; 111 #address-cells = <0>; 112 #size-cells = <0>; 113 #interrupt-cells = <2>; 114 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 115 interrupt-parent = <&UIC0>; 116 }; 117 118 SDR0: sdr { 119 compatible = "ibm,sdr-460gt"; 120 dcr-reg = <0x00e 0x002>; 121 }; 122 123 CPR0: cpr { 124 compatible = "ibm,cpr-460gt"; 125 dcr-reg = <0x00c 0x002>; 126 }; 127 128 L2C0: l2c { 129 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; 130 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 131 0x030 0x008>; /* L2 cache DCR's */ 132 cache-line-size = <32>; /* 32 bytes */ 133 cache-size = <262144>; /* L2, 256K */ 134 interrupt-parent = <&UIC1>; 135 interrupts = <11 1>; 136 }; 137 138 plb { 139 compatible = "ibm,plb-460gt", "ibm,plb4"; 140 #address-cells = <2>; 141 #size-cells = <1>; 142 ranges; 143 clock-frequency = <0>; /* Filled in by U-Boot */ 144 145 SDRAM0: sdram { 146 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; 147 dcr-reg = <0x010 0x002>; 148 }; 149 150 CRYPTO: crypto@180000 { 151 compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto"; 152 reg = <4 0x00180000 0x80400>; 153 interrupt-parent = <&UIC0>; 154 interrupts = <0x1d 0x4>; 155 }; 156 157 MAL0: mcmal { 158 compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 159 dcr-reg = <0x180 0x062>; 160 num-tx-chans = <3>; 161 num-rx-chans = <24>; 162 #address-cells = <0>; 163 #size-cells = <0>; 164 interrupt-parent = <&UIC2>; 165 interrupts = < /*TXEOB*/ 0x6 0x4 166 /*RXEOB*/ 0x7 0x4 167 /*SERR*/ 0x3 0x4 168 /*TXDE*/ 0x4 0x4 169 /*RXDE*/ 0x5 0x4>; 170 desc-base-addr-high = <0x8>; 171 }; 172 173 POB0: opb { 174 compatible = "ibm,opb-460gt", "ibm,opb"; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 178 clock-frequency = <0>; /* Filled in by U-Boot */ 179 180 EBC0: ebc { 181 compatible = "ibm,ebc-460gt", "ibm,ebc"; 182 dcr-reg = <0x012 0x002>; 183 #address-cells = <2>; 184 #size-cells = <1>; 185 clock-frequency = <0>; /* Filled in by U-Boot */ 186 /* ranges property is supplied by U-Boot */ 187 interrupts = <0x6 0x4>; 188 interrupt-parent = <&UIC1>; 189 190 nor_flash@0,0 { 191 compatible = "amd,s29gl256n", "cfi-flash"; 192 bank-width = <2>; 193 reg = <0x00000000 0x00000000 0x02000000>; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 partition@0 { 197 label = "kernel"; 198 reg = <0x00000000 0x001e0000>; 199 }; 200 partition@1e0000 { 201 label = "dtb"; 202 reg = <0x001e0000 0x00020000>; 203 }; 204 partition@200000 { 205 label = "root"; 206 reg = <0x00200000 0x00200000>; 207 }; 208 partition@400000 { 209 label = "user"; 210 reg = <0x00400000 0x01b60000>; 211 }; 212 partition@1f60000 { 213 label = "env"; 214 reg = <0x01f60000 0x00040000>; 215 }; 216 partition@1fa0000 { 217 label = "u-boot"; 218 reg = <0x01fa0000 0x00060000>; 219 }; 220 }; 221 }; 222 223 UART0: serial@ef600300 { 224 device_type = "serial"; 225 compatible = "ns16550"; 226 reg = <0xef600300 0x00000008>; 227 virtual-reg = <0xef600300>; 228 clock-frequency = <0>; /* Filled in by U-Boot */ 229 current-speed = <0>; /* Filled in by U-Boot */ 230 interrupt-parent = <&UIC1>; 231 interrupts = <0x1 0x4>; 232 }; 233 234 IIC0: i2c@ef600700 { 235 compatible = "ibm,iic-460gt", "ibm,iic"; 236 reg = <0xef600700 0x00000014>; 237 interrupt-parent = <&UIC0>; 238 interrupts = <0x2 0x4>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 sttm@4a { 242 compatible = "ad,ad7414"; 243 reg = <0x4a>; 244 interrupt-parent = <&UIC1>; 245 interrupts = <0x0 0x8>; 246 }; 247 }; 248 249 IIC1: i2c@ef600800 { 250 compatible = "ibm,iic-460gt", "ibm,iic"; 251 reg = <0xef600800 0x00000014>; 252 interrupt-parent = <&UIC0>; 253 interrupts = <0x3 0x4>; 254 }; 255 256 TAH0: emac-tah@ef601350 { 257 compatible = "ibm,tah-460gt", "ibm,tah"; 258 reg = <0xef601350 0x00000030>; 259 }; 260 261 TAH1: emac-tah@ef601450 { 262 compatible = "ibm,tah-460gt", "ibm,tah"; 263 reg = <0xef601450 0x00000030>; 264 }; 265 266 EMAC0: ethernet@ef600e00 { 267 device_type = "network"; 268 compatible = "ibm,emac-460gt", "ibm,emac4sync"; 269 interrupt-parent = <&EMAC0>; 270 interrupts = <0x0 0x1>; 271 #interrupt-cells = <1>; 272 #address-cells = <0>; 273 #size-cells = <0>; 274 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 275 /*Wake*/ 0x1 &UIC2 0x14 0x4>; 276 reg = <0xef600e00 0x000000c4>; 277 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 278 mal-device = <&MAL0>; 279 mal-tx-channel = <0>; 280 mal-rx-channel = <0>; 281 cell-index = <0>; 282 max-frame-size = <9000>; 283 rx-fifo-size = <4096>; 284 tx-fifo-size = <2048>; 285 rx-fifo-size-gige = <16384>; 286 phy-mode = "sgmii"; 287 phy-map = <0xffffffff>; 288 gpcs-address = <0x0000000a>; 289 tah-device = <&TAH0>; 290 tah-channel = <0>; 291 has-inverted-stacr-oc; 292 has-new-stacr-staopc; 293 }; 294 295 EMAC1: ethernet@ef600f00 { 296 device_type = "network"; 297 compatible = "ibm,emac-460gt", "ibm,emac4sync"; 298 interrupt-parent = <&EMAC1>; 299 interrupts = <0x0 0x1>; 300 #interrupt-cells = <1>; 301 #address-cells = <0>; 302 #size-cells = <0>; 303 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 304 /*Wake*/ 0x1 &UIC2 0x15 0x4>; 305 reg = <0xef600f00 0x000000c4>; 306 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 307 mal-device = <&MAL0>; 308 mal-tx-channel = <1>; 309 mal-rx-channel = <8>; 310 cell-index = <1>; 311 max-frame-size = <9000>; 312 rx-fifo-size = <4096>; 313 tx-fifo-size = <2048>; 314 rx-fifo-size-gige = <16384>; 315 phy-mode = "sgmii"; 316 phy-map = <0x00000000>; 317 gpcs-address = <0x0000000b>; 318 tah-device = <&TAH1>; 319 tah-channel = <1>; 320 has-inverted-stacr-oc; 321 has-new-stacr-staopc; 322 mdio-device = <&EMAC0>; 323 }; 324 325 EMAC2: ethernet@ef601100 { 326 device_type = "network"; 327 compatible = "ibm,emac-460gt", "ibm,emac4sync"; 328 interrupt-parent = <&EMAC2>; 329 interrupts = <0x0 0x1>; 330 #interrupt-cells = <1>; 331 #address-cells = <0>; 332 #size-cells = <0>; 333 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 334 /*Wake*/ 0x1 &UIC2 0x16 0x4>; 335 reg = <0xef601100 0x000000c4>; 336 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 337 mal-device = <&MAL0>; 338 mal-tx-channel = <2>; 339 mal-rx-channel = <16>; 340 cell-index = <2>; 341 max-frame-size = <9000>; 342 rx-fifo-size = <4096>; 343 tx-fifo-size = <2048>; 344 rx-fifo-size-gige = <16384>; 345 tx-fifo-size-gige = <16384>; /* emac2&3 only */ 346 phy-mode = "sgmii"; 347 phy-map = <0x00000001>; 348 gpcs-address = <0x0000000C>; 349 has-inverted-stacr-oc; 350 has-new-stacr-staopc; 351 mdio-device = <&EMAC0>; 352 }; 353 }; 354 }; 355}; 356