1 #ifndef _PPC_BOOT_DCR_H_ 2 #define _PPC_BOOT_DCR_H_ 3 4 #define mfdcr(rn) \ 5 ({ \ 6 unsigned long rval; \ 7 asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \ 8 rval; \ 9 }) 10 #define mtdcr(rn, val) \ 11 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val)) 12 13 /* 440GP/440GX SDRAM controller DCRs */ 14 #define DCRN_SDRAM0_CFGADDR 0x010 15 #define DCRN_SDRAM0_CFGDATA 0x011 16 17 #define SDRAM0_B0CR 0x40 18 #define SDRAM0_B1CR 0x44 19 #define SDRAM0_B2CR 0x48 20 #define SDRAM0_B3CR 0x4c 21 22 static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR }; 23 24 #define SDRAM_CONFIG_BANK_ENABLE 0x00000001 25 #define SDRAM_CONFIG_SIZE_MASK 0x000e0000 26 #define SDRAM_CONFIG_BANK_SIZE(reg) \ 27 (0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)) 28 29 /* 440GP External Bus Controller (EBC) */ 30 #define DCRN_EBC0_CFGADDR 0x012 31 #define DCRN_EBC0_CFGDATA 0x013 32 #define EBC_NUM_BANKS 8 33 #define EBC_B0CR 0x00 34 #define EBC_B1CR 0x01 35 #define EBC_B2CR 0x02 36 #define EBC_B3CR 0x03 37 #define EBC_B4CR 0x04 38 #define EBC_B5CR 0x05 39 #define EBC_B6CR 0x06 40 #define EBC_B7CR 0x07 41 #define EBC_BXCR(n) (n) 42 #define EBC_BXCR_BAS 0xfff00000 43 #define EBC_BXCR_BS 0x000e0000 44 #define EBC_BXCR_BANK_SIZE(reg) \ 45 (0x100000 << (((reg) & EBC_BXCR_BS) >> 17)) 46 #define EBC_BXCR_BU 0x00018000 47 #define EBC_BXCR_BU_OFF 0x00000000 48 #define EBC_BXCR_BU_RO 0x00008000 49 #define EBC_BXCR_BU_WO 0x00010000 50 #define EBC_BXCR_BU_RW 0x00018000 51 #define EBC_BXCR_BW 0x00006000 52 #define EBC_B0AP 0x10 53 #define EBC_B1AP 0x11 54 #define EBC_B2AP 0x12 55 #define EBC_B3AP 0x13 56 #define EBC_B4AP 0x14 57 #define EBC_B5AP 0x15 58 #define EBC_B6AP 0x16 59 #define EBC_B7AP 0x17 60 #define EBC_BXAP(n) (0x10+(n)) 61 #define EBC_BEAR 0x20 62 #define EBC_BESR 0x21 63 #define EBC_CFG 0x23 64 #define EBC_CID 0x24 65 66 /* 440GP Clock, PM, chip control */ 67 #define DCRN_CPC0_SR 0x0b0 68 #define DCRN_CPC0_ER 0x0b1 69 #define DCRN_CPC0_FR 0x0b2 70 #define DCRN_CPC0_SYS0 0x0e0 71 #define CPC0_SYS0_TUNE 0xffc00000 72 #define CPC0_SYS0_FBDV_MASK 0x003c0000 73 #define CPC0_SYS0_FWDVA_MASK 0x00038000 74 #define CPC0_SYS0_FWDVB_MASK 0x00007000 75 #define CPC0_SYS0_OPDV_MASK 0x00000c00 76 #define CPC0_SYS0_EPDV_MASK 0x00000300 77 /* Helper macros to compute the actual clock divider values from the 78 * encodings in the CPC0 register */ 79 #define CPC0_SYS0_FBDV(reg) \ 80 ((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1) 81 #define CPC0_SYS0_FWDVA(reg) \ 82 (8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15)) 83 #define CPC0_SYS0_FWDVB(reg) \ 84 (8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12)) 85 #define CPC0_SYS0_OPDV(reg) \ 86 ((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1) 87 #define CPC0_SYS0_EPDV(reg) \ 88 ((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1) 89 #define CPC0_SYS0_EXTSL 0x00000080 90 #define CPC0_SYS0_RW_MASK 0x00000060 91 #define CPC0_SYS0_RL 0x00000010 92 #define CPC0_SYS0_ZMIISL_MASK 0x0000000c 93 #define CPC0_SYS0_BYPASS 0x00000002 94 #define CPC0_SYS0_NTO1 0x00000001 95 #define DCRN_CPC0_SYS1 0x0e1 96 #define DCRN_CPC0_CUST0 0x0e2 97 #define DCRN_CPC0_CUST1 0x0e3 98 #define DCRN_CPC0_STRP0 0x0e4 99 #define DCRN_CPC0_STRP1 0x0e5 100 #define DCRN_CPC0_STRP2 0x0e6 101 #define DCRN_CPC0_STRP3 0x0e7 102 #define DCRN_CPC0_GPIO 0x0e8 103 #define DCRN_CPC0_PLB 0x0e9 104 #define DCRN_CPC0_CR1 0x0ea 105 #define DCRN_CPC0_CR0 0x0eb 106 #define CPC0_CR0_SWE 0x80000000 107 #define CPC0_CR0_CETE 0x40000000 108 #define CPC0_CR0_U1FCS 0x20000000 109 #define CPC0_CR0_U0DTE 0x10000000 110 #define CPC0_CR0_U0DRE 0x08000000 111 #define CPC0_CR0_U0DC 0x04000000 112 #define CPC0_CR0_U1DTE 0x02000000 113 #define CPC0_CR0_U1DRE 0x01000000 114 #define CPC0_CR0_U1DC 0x00800000 115 #define CPC0_CR0_U0EC 0x00400000 116 #define CPC0_CR0_U1EC 0x00200000 117 #define CPC0_CR0_UDIV_MASK 0x001f0000 118 #define CPC0_CR0_UDIV(reg) \ 119 ((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1) 120 #define DCRN_CPC0_MIRQ0 0x0ec 121 #define DCRN_CPC0_MIRQ1 0x0ed 122 #define DCRN_CPC0_JTAGID 0x0ef 123 124 #endif /* _PPC_BOOT_DCR_H_ */ 125