1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Old U-boot compatibility for PowerQUICC II 4 * (a.k.a. 82xx with CPM, not the 8240 family of chips) 5 * 6 * Author: Scott Wood <scottwood@freescale.com> 7 * 8 * Copyright (c) 2007 Freescale Semiconductor, Inc. 9 */ 10 11 #include "ops.h" 12 #include "stdio.h" 13 #include "cuboot.h" 14 #include "io.h" 15 #include "fsl-soc.h" 16 17 #define TARGET_CPM2 18 #define TARGET_HAS_ETH1 19 #include "ppcboot.h" 20 21 static bd_t bd; 22 23 struct cs_range { 24 u32 csnum; 25 u32 base; /* must be zero */ 26 u32 addr; 27 u32 size; 28 }; 29 30 struct pci_range { 31 u32 flags; 32 u32 pci_addr[2]; 33 u32 phys_addr; 34 u32 size[2]; 35 }; 36 37 struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)]; 38 struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)]; 39 40 /* Different versions of u-boot put the BCSR in different places, and 41 * some don't set up the PCI PIC at all, so we assume the device tree is 42 * sane and update the BRx registers appropriately. 43 * 44 * For any node defined as compatible with fsl,pq2-localbus, 45 * #address/#size must be 2/1 for the localbus, and 1/1 for the parent bus. 46 * Ranges must be for whole chip selects. 47 */ 48 static void update_cs_ranges(void) 49 { 50 void *bus_node, *parent_node; 51 u32 *ctrl_addr; 52 unsigned long ctrl_size; 53 u32 naddr, nsize; 54 int len; 55 int i; 56 57 bus_node = finddevice("/localbus"); 58 if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus")) 59 return; 60 61 dt_get_reg_format(bus_node, &naddr, &nsize); 62 if (naddr != 2 || nsize != 1) 63 goto err; 64 65 parent_node = get_parent(bus_node); 66 if (!parent_node) 67 goto err; 68 69 dt_get_reg_format(parent_node, &naddr, &nsize); 70 if (naddr != 1 || nsize != 1) 71 goto err; 72 73 if (!dt_xlate_reg(bus_node, 0, (unsigned long *)&ctrl_addr, 74 &ctrl_size)) 75 goto err; 76 77 len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf)); 78 79 for (i = 0; i < len / sizeof(struct cs_range); i++) { 80 u32 base, option; 81 int cs = cs_ranges_buf[i].csnum; 82 if (cs >= ctrl_size / 8) 83 goto err; 84 85 if (cs_ranges_buf[i].base != 0) 86 goto err; 87 88 base = in_be32(&ctrl_addr[cs * 2]); 89 90 /* If CS is already valid, use the existing flags. 91 * Otherwise, guess a sane default. 92 */ 93 if (base & 1) { 94 base &= 0x7fff; 95 option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff; 96 } else { 97 base = 0x1801; 98 option = 0x10; 99 } 100 101 out_be32(&ctrl_addr[cs * 2], 0); 102 out_be32(&ctrl_addr[cs * 2 + 1], 103 option | ~(cs_ranges_buf[i].size - 1)); 104 out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr); 105 } 106 107 return; 108 109 err: 110 printf("Bad /localbus node\r\n"); 111 } 112 113 /* Older u-boots don't set PCI up properly. Update the hardware to match 114 * the device tree. The prefetch mem region and non-prefetch mem region 115 * must be contiguous in the host bus. As required by the PCI binding, 116 * PCI #addr/#size must be 3/2. The parent bus must be 1/1. Only 117 * 32-bit PCI is supported. All three region types (prefetchable mem, 118 * non-prefetchable mem, and I/O) must be present. 119 */ 120 static void fixup_pci(void) 121 { 122 struct pci_range *mem = NULL, *mmio = NULL, 123 *io = NULL, *mem_base = NULL; 124 u32 *pci_regs[3]; 125 u8 *soc_regs; 126 int i, len; 127 void *node, *parent_node; 128 u32 naddr, nsize, mem_pow2, mem_mask; 129 130 node = finddevice("/pci"); 131 if (!node || !dt_is_compatible(node, "fsl,pq2-pci")) 132 return; 133 134 for (i = 0; i < 3; i++) 135 if (!dt_xlate_reg(node, i, 136 (unsigned long *)&pci_regs[i], NULL)) 137 goto err; 138 139 soc_regs = (u8 *)fsl_get_immr(); 140 if (!soc_regs) 141 goto unhandled; 142 143 dt_get_reg_format(node, &naddr, &nsize); 144 if (naddr != 3 || nsize != 2) 145 goto err; 146 147 parent_node = get_parent(node); 148 if (!parent_node) 149 goto err; 150 151 dt_get_reg_format(parent_node, &naddr, &nsize); 152 if (naddr != 1 || nsize != 1) 153 goto unhandled; 154 155 len = getprop(node, "ranges", pci_ranges_buf, 156 sizeof(pci_ranges_buf)); 157 158 for (i = 0; i < len / sizeof(struct pci_range); i++) { 159 u32 flags = pci_ranges_buf[i].flags & 0x43000000; 160 161 if (flags == 0x42000000) 162 mem = &pci_ranges_buf[i]; 163 else if (flags == 0x02000000) 164 mmio = &pci_ranges_buf[i]; 165 else if (flags == 0x01000000) 166 io = &pci_ranges_buf[i]; 167 } 168 169 if (!mem || !mmio || !io) 170 goto unhandled; 171 if (mem->size[1] != mmio->size[1]) 172 goto unhandled; 173 if (mem->size[1] & (mem->size[1] - 1)) 174 goto unhandled; 175 if (io->size[1] & (io->size[1] - 1)) 176 goto unhandled; 177 178 if (mem->phys_addr + mem->size[1] == mmio->phys_addr) 179 mem_base = mem; 180 else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr) 181 mem_base = mmio; 182 else 183 goto unhandled; 184 185 out_be32(&pci_regs[1][0], mem_base->phys_addr | 1); 186 out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1)); 187 188 out_be32(&pci_regs[1][1], io->phys_addr | 1); 189 out_be32(&pci_regs[2][1], ~(io->size[1] - 1)); 190 191 out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12); 192 out_le32(&pci_regs[0][2], mem->phys_addr >> 12); 193 out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000); 194 195 out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12); 196 out_le32(&pci_regs[0][8], mmio->phys_addr >> 12); 197 out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000); 198 199 out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12); 200 out_le32(&pci_regs[0][14], io->phys_addr >> 12); 201 out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000); 202 203 /* Inbound translation */ 204 out_le32(&pci_regs[0][58], 0); 205 out_le32(&pci_regs[0][60], 0); 206 207 mem_pow2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1); 208 mem_mask = ~(mem_pow2 - 1) >> 12; 209 out_le32(&pci_regs[0][62], 0xa0000000 | mem_mask); 210 211 /* If PCI is disabled, drive RST high to enable. */ 212 if (!(in_le32(&pci_regs[0][32]) & 1)) { 213 /* Tpvrh (Power valid to RST# high) 100 ms */ 214 udelay(100000); 215 216 out_le32(&pci_regs[0][32], 1); 217 218 /* Trhfa (RST# high to first cfg access) 2^25 clocks */ 219 udelay(1020000); 220 } 221 222 /* Enable bus master and memory access */ 223 out_le32(&pci_regs[0][64], 0x80000004); 224 out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6); 225 226 /* Park the bus on PCI, and elevate PCI's arbitration priority, 227 * as required by section 9.6 of the user's manual. 228 */ 229 out_8(&soc_regs[0x10028], 3); 230 out_be32((u32 *)&soc_regs[0x1002c], 0x01236745); 231 232 return; 233 234 err: 235 printf("Bad PCI node -- using existing firmware setup.\r\n"); 236 return; 237 238 unhandled: 239 printf("Unsupported PCI node -- using existing firmware setup.\r\n"); 240 } 241 242 static void pq2_platform_fixups(void) 243 { 244 void *node; 245 246 dt_fixup_memory(bd.bi_memstart, bd.bi_memsize); 247 dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr); 248 dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq); 249 250 node = finddevice("/soc/cpm"); 251 if (node) 252 setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4); 253 254 node = finddevice("/soc/cpm/brg"); 255 if (node) 256 setprop(node, "clock-frequency", &bd.bi_brgfreq, 4); 257 258 update_cs_ranges(); 259 fixup_pci(); 260 } 261 262 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, 263 unsigned long r6, unsigned long r7) 264 { 265 CUBOOT_INIT(); 266 fdt_init(_dtb_start); 267 serial_console_init(); 268 platform_ops.fixups = pq2_platform_fixups; 269 } 270