1660662f8SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
21da177e4SLinus Torvalds /*
31da177e4SLinus Torvalds * Linux/PA-RISC Project (http://www.parisc-linux.org/)
41da177e4SLinus Torvalds *
51da177e4SLinus Torvalds * Floating-point emulation code
61da177e4SLinus Torvalds * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
71da177e4SLinus Torvalds */
81da177e4SLinus Torvalds /*
91da177e4SLinus Torvalds * BEGIN_DESC
101da177e4SLinus Torvalds *
111da177e4SLinus Torvalds * File:
121da177e4SLinus Torvalds * @(#) pa/fp/decode_exc.c $ Revision: $
131da177e4SLinus Torvalds *
141da177e4SLinus Torvalds * Purpose:
151da177e4SLinus Torvalds * <<please update with a synopsis of the functionality provided by this file>>
161da177e4SLinus Torvalds *
171da177e4SLinus Torvalds * External Interfaces:
181da177e4SLinus Torvalds * <<the following list was autogenerated, please review>>
191da177e4SLinus Torvalds * decode_fpu(Fpu_register, trap_counts)
201da177e4SLinus Torvalds *
211da177e4SLinus Torvalds * Internal Interfaces:
221da177e4SLinus Torvalds * <<please update>>
231da177e4SLinus Torvalds *
241da177e4SLinus Torvalds * Theory:
251da177e4SLinus Torvalds * <<please update with a overview of the operation of this file>>
261da177e4SLinus Torvalds *
271da177e4SLinus Torvalds * END_DESC
281da177e4SLinus Torvalds */
291da177e4SLinus Torvalds
30e9b26010SAlexander Beregalov #include <linux/kernel.h>
311da177e4SLinus Torvalds #include "float.h"
321da177e4SLinus Torvalds #include "sgl_float.h"
331da177e4SLinus Torvalds #include "dbl_float.h"
341da177e4SLinus Torvalds #include "cnv_float.h"
351da177e4SLinus Torvalds /* #include "types.h" */
361da177e4SLinus Torvalds #include <asm/signal.h>
371da177e4SLinus Torvalds #include <asm/siginfo.h>
381da177e4SLinus Torvalds /* #include <machine/sys/mdep_private.h> */
391da177e4SLinus Torvalds
401da177e4SLinus Torvalds #undef Fpustatus_register
411da177e4SLinus Torvalds #define Fpustatus_register Fpu_register[0]
421da177e4SLinus Torvalds
431da177e4SLinus Torvalds /* General definitions */
441da177e4SLinus Torvalds #define DOESTRAP 1
451da177e4SLinus Torvalds #define NOTRAP 0
46497888cfSPhil Carmody #define SIGNALCODE(signal, code) ((signal) << 24 | (code))
471da177e4SLinus Torvalds #define copropbit 1<<31-2 /* bit position 2 */
481da177e4SLinus Torvalds #define opclass 9 /* bits 21 & 22 */
49*7f2dcc73SKees Cook #define fmtbits 11 /* bits 19 & 20 */
501da177e4SLinus Torvalds #define df 13 /* bits 17 & 18 */
511da177e4SLinus Torvalds #define twobits 3 /* mask low-order 2 bits */
521da177e4SLinus Torvalds #define fivebits 31 /* mask low-order 5 bits */
531da177e4SLinus Torvalds #define MAX_EXCP_REG 7 /* number of excpeption registers to check */
541da177e4SLinus Torvalds
551da177e4SLinus Torvalds /* Exception register definitions */
561da177e4SLinus Torvalds #define Excp_type(index) Exceptiontype(Fpu_register[index])
571da177e4SLinus Torvalds #define Excp_instr(index) Instructionfield(Fpu_register[index])
581da177e4SLinus Torvalds #define Clear_excp_register(index) Allexception(Fpu_register[index]) = 0
591da177e4SLinus Torvalds #define Excp_format() \
60*7f2dcc73SKees Cook (current_ir >> ((current_ir>>opclass & twobits) == 1 ? df : fmtbits) & twobits)
611da177e4SLinus Torvalds
621da177e4SLinus Torvalds /* Miscellaneous definitions */
631da177e4SLinus Torvalds #define Fpu_sgl(index) Fpu_register[index*2]
641da177e4SLinus Torvalds
651da177e4SLinus Torvalds #define Fpu_dblp1(index) Fpu_register[index*2]
661da177e4SLinus Torvalds #define Fpu_dblp2(index) Fpu_register[(index*2)+1]
671da177e4SLinus Torvalds
681da177e4SLinus Torvalds #define Fpu_quadp1(index) Fpu_register[index*2]
691da177e4SLinus Torvalds #define Fpu_quadp2(index) Fpu_register[(index*2)+1]
701da177e4SLinus Torvalds #define Fpu_quadp3(index) Fpu_register[(index*2)+2]
711da177e4SLinus Torvalds #define Fpu_quadp4(index) Fpu_register[(index*2)+3]
721da177e4SLinus Torvalds
731da177e4SLinus Torvalds /* Single precision floating-point definitions */
741da177e4SLinus Torvalds #ifndef Sgl_decrement
751da177e4SLinus Torvalds # define Sgl_decrement(sgl_value) Sall(sgl_value)--
761da177e4SLinus Torvalds #endif
771da177e4SLinus Torvalds
781da177e4SLinus Torvalds /* Double precision floating-point definitions */
791da177e4SLinus Torvalds #ifndef Dbl_decrement
801da177e4SLinus Torvalds # define Dbl_decrement(dbl_valuep1,dbl_valuep2) \
811da177e4SLinus Torvalds if ((Dallp2(dbl_valuep2)--) == 0) Dallp1(dbl_valuep1)--
821da177e4SLinus Torvalds #endif
831da177e4SLinus Torvalds
841da177e4SLinus Torvalds
851da177e4SLinus Torvalds #define update_trap_counts(Fpu_register, aflags, bflags, trap_counts) { \
861da177e4SLinus Torvalds aflags=(Fpu_register[0])>>27; /* assumes zero fill. 32 bit */ \
871da177e4SLinus Torvalds Fpu_register[0] |= bflags; \
881da177e4SLinus Torvalds }
891da177e4SLinus Torvalds
901da177e4SLinus Torvalds u_int
decode_fpu(unsigned int Fpu_register[],unsigned int trap_counts[])911da177e4SLinus Torvalds decode_fpu(unsigned int Fpu_register[], unsigned int trap_counts[])
921da177e4SLinus Torvalds {
931da177e4SLinus Torvalds unsigned int current_ir, excp;
941da177e4SLinus Torvalds int target, exception_index = 1;
951da177e4SLinus Torvalds boolean inexact;
961da177e4SLinus Torvalds unsigned int aflags;
971da177e4SLinus Torvalds unsigned int bflags;
981da177e4SLinus Torvalds unsigned int excptype;
991da177e4SLinus Torvalds
1001da177e4SLinus Torvalds
1011da177e4SLinus Torvalds /* Keep stats on how many floating point exceptions (based on type)
1021da177e4SLinus Torvalds * that happen. Want to keep this overhead low, but still provide
1031da177e4SLinus Torvalds * some information to the customer. All exits from this routine
1041da177e4SLinus Torvalds * need to restore Fpu_register[0]
1051da177e4SLinus Torvalds */
1061da177e4SLinus Torvalds
1071da177e4SLinus Torvalds bflags=(Fpu_register[0] & 0xf8000000);
1081da177e4SLinus Torvalds Fpu_register[0] &= 0x07ffffff;
1091da177e4SLinus Torvalds
1101da177e4SLinus Torvalds /* exception_index is used to index the exception register queue. It
1111da177e4SLinus Torvalds * always points at the last register that contains a valid exception. A
1121da177e4SLinus Torvalds * zero value implies no exceptions (also the initialized value). Setting
1131da177e4SLinus Torvalds * the T-bit resets the exception_index to zero.
1141da177e4SLinus Torvalds */
1151da177e4SLinus Torvalds
1161da177e4SLinus Torvalds /*
1171da177e4SLinus Torvalds * Check for reserved-op exception. A reserved-op exception does not
1181da177e4SLinus Torvalds * set any exception registers nor does it set the T-bit. If the T-bit
1191da177e4SLinus Torvalds * is not set then a reserved-op exception occurred.
1201da177e4SLinus Torvalds *
1211da177e4SLinus Torvalds * At some point, we may want to report reserved op exceptions as
1221da177e4SLinus Torvalds * illegal instructions.
1231da177e4SLinus Torvalds */
1241da177e4SLinus Torvalds
1251da177e4SLinus Torvalds if (!Is_tbit_set()) {
1261da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
1271da177e4SLinus Torvalds return SIGNALCODE(SIGILL, ILL_COPROC);
1281da177e4SLinus Torvalds }
1291da177e4SLinus Torvalds
1301da177e4SLinus Torvalds /*
1311da177e4SLinus Torvalds * Is a coprocessor op.
1321da177e4SLinus Torvalds *
1331da177e4SLinus Torvalds * Now we need to determine what type of exception occurred.
1341da177e4SLinus Torvalds */
1351da177e4SLinus Torvalds for (exception_index=1; exception_index<=MAX_EXCP_REG; exception_index++) {
1361da177e4SLinus Torvalds current_ir = Excp_instr(exception_index);
1371da177e4SLinus Torvalds /*
1381da177e4SLinus Torvalds * On PA89: there are 5 different unimplemented exception
1391da177e4SLinus Torvalds * codes: 0x1, 0x9, 0xb, 0x3, and 0x23. PA-RISC 2.0 adds
1401da177e4SLinus Torvalds * another, 0x2b. Only these have the low order bit set.
1411da177e4SLinus Torvalds */
1421da177e4SLinus Torvalds excptype = Excp_type(exception_index);
1431da177e4SLinus Torvalds if (excptype & UNIMPLEMENTEDEXCEPTION) {
1441da177e4SLinus Torvalds /*
1451da177e4SLinus Torvalds * Clear T-bit and exception register so that
1461da177e4SLinus Torvalds * we can tell if a trap really occurs while
1471da177e4SLinus Torvalds * emulating the instruction.
1481da177e4SLinus Torvalds */
1491da177e4SLinus Torvalds Clear_tbit();
1501da177e4SLinus Torvalds Clear_excp_register(exception_index);
1511da177e4SLinus Torvalds /*
1521da177e4SLinus Torvalds * Now emulate this instruction. If a trap occurs,
1531da177e4SLinus Torvalds * fpudispatch will return a non-zero number
1541da177e4SLinus Torvalds */
1551da177e4SLinus Torvalds excp = fpudispatch(current_ir,excptype,0,Fpu_register);
1561da177e4SLinus Torvalds /* accumulate the status flags, don't lose them as in hpux */
1571da177e4SLinus Torvalds if (excp) {
1581da177e4SLinus Torvalds /*
1591da177e4SLinus Torvalds * We now need to make sure that the T-bit and the
1601da177e4SLinus Torvalds * exception register contain the correct values
1611da177e4SLinus Torvalds * before continuing.
1621da177e4SLinus Torvalds */
1631da177e4SLinus Torvalds /*
1641da177e4SLinus Torvalds * Set t-bit since it might still be needed for a
1651da177e4SLinus Torvalds * subsequent real trap (I don't understand fully -PB)
1661da177e4SLinus Torvalds */
1671da177e4SLinus Torvalds Set_tbit();
1681da177e4SLinus Torvalds /* some of the following code uses
1691da177e4SLinus Torvalds * Excp_type(exception_index) so fix that up */
1701da177e4SLinus Torvalds Set_exceptiontype_and_instr_field(excp,current_ir,
1711da177e4SLinus Torvalds Fpu_register[exception_index]);
1721da177e4SLinus Torvalds if (excp == UNIMPLEMENTEDEXCEPTION) {
1731da177e4SLinus Torvalds /*
1741da177e4SLinus Torvalds * it is really unimplemented, so restore the
1751da177e4SLinus Torvalds * TIMEX extended unimplemented exception code
1761da177e4SLinus Torvalds */
1771da177e4SLinus Torvalds excp = excptype;
1781da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags,
1791da177e4SLinus Torvalds trap_counts);
1801da177e4SLinus Torvalds return SIGNALCODE(SIGILL, ILL_COPROC);
1811da177e4SLinus Torvalds }
1821da177e4SLinus Torvalds /* some of the following code uses excptype, so
1831da177e4SLinus Torvalds * fix that up too */
1841da177e4SLinus Torvalds excptype = excp;
1851da177e4SLinus Torvalds }
1861da177e4SLinus Torvalds /* handle exceptions other than the real UNIMPLIMENTED the
1871da177e4SLinus Torvalds * same way as if the hardware had caused them */
1881da177e4SLinus Torvalds if (excp == NOEXCEPTION)
1891da177e4SLinus Torvalds /* For now use 'break', should technically be 'continue' */
1901da177e4SLinus Torvalds break;
1911da177e4SLinus Torvalds }
1921da177e4SLinus Torvalds
1931da177e4SLinus Torvalds /*
1941da177e4SLinus Torvalds * In PA89, the underflow exception has been extended to encode
1951da177e4SLinus Torvalds * additional information. The exception looks like pp01x0,
1961da177e4SLinus Torvalds * where x is 1 if inexact and pp represent the inexact bit (I)
1971da177e4SLinus Torvalds * and the round away bit (RA)
1981da177e4SLinus Torvalds */
1991da177e4SLinus Torvalds if (excptype & UNDERFLOWEXCEPTION) {
2001da177e4SLinus Torvalds /* check for underflow trap enabled */
2011da177e4SLinus Torvalds if (Is_underflowtrap_enabled()) {
2021da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags,
2031da177e4SLinus Torvalds trap_counts);
2041da177e4SLinus Torvalds return SIGNALCODE(SIGFPE, FPE_FLTUND);
2051da177e4SLinus Torvalds } else {
2061da177e4SLinus Torvalds /*
2071da177e4SLinus Torvalds * Isn't a real trap; we need to
2081da177e4SLinus Torvalds * return the default value.
2091da177e4SLinus Torvalds */
2101da177e4SLinus Torvalds target = current_ir & fivebits;
2111da177e4SLinus Torvalds #ifndef lint
2121da177e4SLinus Torvalds if (Ibit(Fpu_register[exception_index])) inexact = TRUE;
2131da177e4SLinus Torvalds else inexact = FALSE;
2141da177e4SLinus Torvalds #endif
2151da177e4SLinus Torvalds switch (Excp_format()) {
2161da177e4SLinus Torvalds case SGL:
2171da177e4SLinus Torvalds /*
2181da177e4SLinus Torvalds * If ra (round-away) is set, will
2191da177e4SLinus Torvalds * want to undo the rounding done
2201da177e4SLinus Torvalds * by the hardware.
2211da177e4SLinus Torvalds */
2221da177e4SLinus Torvalds if (Rabit(Fpu_register[exception_index]))
2231da177e4SLinus Torvalds Sgl_decrement(Fpu_sgl(target));
2241da177e4SLinus Torvalds
2251da177e4SLinus Torvalds /* now denormalize */
2261da177e4SLinus Torvalds sgl_denormalize(&Fpu_sgl(target),&inexact,Rounding_mode());
2271da177e4SLinus Torvalds break;
2281da177e4SLinus Torvalds case DBL:
2291da177e4SLinus Torvalds /*
2301da177e4SLinus Torvalds * If ra (round-away) is set, will
2311da177e4SLinus Torvalds * want to undo the rounding done
2321da177e4SLinus Torvalds * by the hardware.
2331da177e4SLinus Torvalds */
2341da177e4SLinus Torvalds if (Rabit(Fpu_register[exception_index]))
2351da177e4SLinus Torvalds Dbl_decrement(Fpu_dblp1(target),Fpu_dblp2(target));
2361da177e4SLinus Torvalds
2371da177e4SLinus Torvalds /* now denormalize */
2381da177e4SLinus Torvalds dbl_denormalize(&Fpu_dblp1(target),&Fpu_dblp2(target),
2391da177e4SLinus Torvalds &inexact,Rounding_mode());
2401da177e4SLinus Torvalds break;
2411da177e4SLinus Torvalds }
2421da177e4SLinus Torvalds if (inexact) Set_underflowflag();
2431da177e4SLinus Torvalds /*
2441da177e4SLinus Torvalds * Underflow can generate an inexact
2451da177e4SLinus Torvalds * exception. If inexact trap is enabled,
2461da177e4SLinus Torvalds * want to do an inexact trap, otherwise
2471da177e4SLinus Torvalds * set inexact flag.
2481da177e4SLinus Torvalds */
2491da177e4SLinus Torvalds if (inexact && Is_inexacttrap_enabled()) {
2501da177e4SLinus Torvalds /*
2511da177e4SLinus Torvalds * Set exception field of exception register
2521da177e4SLinus Torvalds * to inexact, parm field to zero.
2531da177e4SLinus Torvalds * Underflow bit should be cleared.
2541da177e4SLinus Torvalds */
2551da177e4SLinus Torvalds Set_exceptiontype(Fpu_register[exception_index],
2561da177e4SLinus Torvalds INEXACTEXCEPTION);
2571da177e4SLinus Torvalds Set_parmfield(Fpu_register[exception_index],0);
2581da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags,
2591da177e4SLinus Torvalds trap_counts);
2601da177e4SLinus Torvalds return SIGNALCODE(SIGFPE, FPE_FLTRES);
2611da177e4SLinus Torvalds }
2621da177e4SLinus Torvalds else {
2631da177e4SLinus Torvalds /*
2641da177e4SLinus Torvalds * Exception register needs to be cleared.
2651da177e4SLinus Torvalds * Inexact flag needs to be set if inexact.
2661da177e4SLinus Torvalds */
2671da177e4SLinus Torvalds Clear_excp_register(exception_index);
2681da177e4SLinus Torvalds if (inexact) Set_inexactflag();
2691da177e4SLinus Torvalds }
2701da177e4SLinus Torvalds }
2711da177e4SLinus Torvalds continue;
2721da177e4SLinus Torvalds }
2731da177e4SLinus Torvalds switch(Excp_type(exception_index)) {
2741da177e4SLinus Torvalds case OVERFLOWEXCEPTION:
2751da177e4SLinus Torvalds case OVERFLOWEXCEPTION | INEXACTEXCEPTION:
2761da177e4SLinus Torvalds /* check for overflow trap enabled */
2771da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags,
2781da177e4SLinus Torvalds trap_counts);
2791da177e4SLinus Torvalds if (Is_overflowtrap_enabled()) {
2801da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags,
2811da177e4SLinus Torvalds trap_counts);
2821da177e4SLinus Torvalds return SIGNALCODE(SIGFPE, FPE_FLTOVF);
2831da177e4SLinus Torvalds } else {
2841da177e4SLinus Torvalds /*
2851da177e4SLinus Torvalds * Isn't a real trap; we need to
2861da177e4SLinus Torvalds * return the default value.
2871da177e4SLinus Torvalds */
2881da177e4SLinus Torvalds target = current_ir & fivebits;
2891da177e4SLinus Torvalds switch (Excp_format()) {
2901da177e4SLinus Torvalds case SGL:
2911da177e4SLinus Torvalds Sgl_setoverflow(Fpu_sgl(target));
2921da177e4SLinus Torvalds break;
2931da177e4SLinus Torvalds case DBL:
2941da177e4SLinus Torvalds Dbl_setoverflow(Fpu_dblp1(target),Fpu_dblp2(target));
2951da177e4SLinus Torvalds break;
2961da177e4SLinus Torvalds }
2971da177e4SLinus Torvalds Set_overflowflag();
2981da177e4SLinus Torvalds /*
2991da177e4SLinus Torvalds * Overflow always generates an inexact
3001da177e4SLinus Torvalds * exception. If inexact trap is enabled,
3011da177e4SLinus Torvalds * want to do an inexact trap, otherwise
3021da177e4SLinus Torvalds * set inexact flag.
3031da177e4SLinus Torvalds */
3041da177e4SLinus Torvalds if (Is_inexacttrap_enabled()) {
3051da177e4SLinus Torvalds /*
3061da177e4SLinus Torvalds * Set exception field of exception
3071da177e4SLinus Torvalds * register to inexact. Overflow
3081da177e4SLinus Torvalds * bit should be cleared.
3091da177e4SLinus Torvalds */
3101da177e4SLinus Torvalds Set_exceptiontype(Fpu_register[exception_index],
3111da177e4SLinus Torvalds INEXACTEXCEPTION);
3121da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags,
3131da177e4SLinus Torvalds trap_counts);
3141da177e4SLinus Torvalds return SIGNALCODE(SIGFPE, FPE_FLTRES);
3151da177e4SLinus Torvalds }
3161da177e4SLinus Torvalds else {
3171da177e4SLinus Torvalds /*
3181da177e4SLinus Torvalds * Exception register needs to be cleared.
3191da177e4SLinus Torvalds * Inexact flag needs to be set.
3201da177e4SLinus Torvalds */
3211da177e4SLinus Torvalds Clear_excp_register(exception_index);
3221da177e4SLinus Torvalds Set_inexactflag();
3231da177e4SLinus Torvalds }
3241da177e4SLinus Torvalds }
3251da177e4SLinus Torvalds break;
3261da177e4SLinus Torvalds case INVALIDEXCEPTION:
327370361f8SJames Bottomley case OPC_2E_INVALIDEXCEPTION:
3281da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
3291da177e4SLinus Torvalds return SIGNALCODE(SIGFPE, FPE_FLTINV);
3301da177e4SLinus Torvalds case DIVISIONBYZEROEXCEPTION:
3311da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
332550f0d92SHelge Deller Clear_excp_register(exception_index);
3331da177e4SLinus Torvalds return SIGNALCODE(SIGFPE, FPE_FLTDIV);
3341da177e4SLinus Torvalds case INEXACTEXCEPTION:
3351da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
3361da177e4SLinus Torvalds return SIGNALCODE(SIGFPE, FPE_FLTRES);
3371da177e4SLinus Torvalds default:
3381da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
3391da177e4SLinus Torvalds printk("%s(%d) Unknown FPU exception 0x%x\n", __FILE__,
3401da177e4SLinus Torvalds __LINE__, Excp_type(exception_index));
3411da177e4SLinus Torvalds return SIGNALCODE(SIGILL, ILL_COPROC);
3421da177e4SLinus Torvalds case NOEXCEPTION: /* no exception */
3431da177e4SLinus Torvalds /*
3441da177e4SLinus Torvalds * Clear exception register in case
3451da177e4SLinus Torvalds * other fields are non-zero.
3461da177e4SLinus Torvalds */
3471da177e4SLinus Torvalds Clear_excp_register(exception_index);
3481da177e4SLinus Torvalds break;
3491da177e4SLinus Torvalds }
3501da177e4SLinus Torvalds }
3511da177e4SLinus Torvalds /*
3521da177e4SLinus Torvalds * No real exceptions occurred.
3531da177e4SLinus Torvalds */
3541da177e4SLinus Torvalds Clear_tbit();
3551da177e4SLinus Torvalds update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
3561da177e4SLinus Torvalds return(NOTRAP);
3571da177e4SLinus Torvalds }
358